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AD7944 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7944은 전자 산업 및 응용 분야에서
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부품번호 AD7944 기능
기능 PulSAR 15.5 mW ADC
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AD7944 데이터시트, 핀배열, 회로
14-Bit, 2.5 MSPS, PulSAR
15.5 mW ADC in LFCSP
AD7944
FEATURES
14-bit resolution with no missing codes
Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low)
Low power dissipation
15.5 mW at 2.5 MSPS, with external reference
28 mW at 2.5 MSPS, with internal reference
INL: ±0.25 LSB typical, ±1.0 LSB maximum
SNR
84 dB, with on-chip reference
84.5 dB, with external reference
4.096 V internal reference: typical drift of ±10 ppm/°C
Pseudo differential analog input voltage range
0 V to VREF with VREF up to 5.0 V
Allows use of any input range
No pipeline delay
Logic interface: 1.8 V/2.5 V/2.7 V
Serial interface: SPI-/QSPI-/MICROWIRE-/DSP-compatible
Ability to daisy-chain multiple ADCs with busy indicator
20-lead, 4 mm × 4 mm LFCSP (QFN)
APPLICATIONS
Battery-powered equipment
Communications
ATE
Data acquisition systems
Medical instruments
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0V
TO
VREF
APPLICATION DIAGRAM
1.8V
TO
5V 2.5V 2.7V
BVDD AVDD, VIO
DVDD TURBO
IN+ SDI
AD7944
IN–
SCK
SDO
GND REF
CNV
10µF
VIO
3- OR 4-WIRE
INTERFACE:
SPI, CS,
DAISY CHAIN
(TURBO = LOW)
NOTES
1. GND REFERS TO REFGND, AGND, AND DGND.
Figure 1.
GENERAL DESCRIPTION
The AD7944 is a 14-bit, 2.5 MSPS successive approximation
analog-to-digital converter (SAR ADC). It contains a low power,
high speed, 14-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
a versatile serial interface port. On the rising edge of CNV, the
AD7944 samples an analog input, IN+, between 0 V and VREF
with respect to a ground sense, IN−. The AD7944 features a
very high sampling rate turbo mode (TURBO high) and a
reduced power normal mode (TURBO low) for low power
applications where the power is scaled with the throughput.
In normal mode (TURBO low), the SPI-compatible serial inter-
face also features the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus and provide an optional busy
indicator. The serial interface is compatible with 1.8 V, 2.5 V,
and 2.7 V supplies using the separate VIO supply.
The AD7944 is available in a 20-lead LFCSP with operation
specified from −40°C to +85°C.
Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR® ADCs1
Type
100 kSPS
250 kSPS
14-Bit
AD7940
AD79422
16-Bit
AD7680
AD76852
AD7683
AD76872
AD7684
AD7694
18-Bit
AD76912
400 kSPS to 500 kSPS
AD79462
AD76862
AD76882
AD76932
AD76902
≥1000 kSPS
AD79443
AD79802
AD79832
AD79853
AD79822
AD79842
AD79863
ADC Driver
ADA4941-1
ADA4841-x
AD8021
ADA4941-1
ADA4841-x
AD8021
1 See www.analog.com for the latest selection of PulSAR ADCs and ADC drivers.
2 Pin-for-pin compatible with all other parts marked with this endnote.
3 The AD7944, AD7985, and AD7986 are pin-for-pin compatible.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.




AD7944 pdf, 반도체, 판매, 대치품
AD7944
Table 3.
Parameter
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Turn-On Settling Time
REFIN Output Voltage
REFIN Output Resistance
EXTERNAL REFERENCE
Voltage Range
Current Drain
REFERENCE BUFFER
REFIN Input Voltage
REFIN Input Current
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Test Conditions/Comments
PDREF is low
TA = 25°C
−40°C to +85°C
AVDD = 2.5 V ± 5%
CREF = 10 μF, CREFIN = 0.1 μF
REFIN at 25°C
PDREF is high, REFIN is low
VOL
VOH
POWER SUPPLIES
AVDD, DVDD
BVDD
VIO
Standby Current1, 2
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With Internal Reference
With External Reference
TEMPERATURE RANGE3
Specified Performance
ISINK = +500 μA
ISOURCE = −500 μA
Specified performance
AVDD = DVDD = VIO = 2.5 V
2.5 MSPS throughput
2.0 MSPS throughput
2.5 MSPS throughput
2.0 MSPS throughput
TMIN to TMAX
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Min
4.081
2.4
Typ
4.096
±10
±50
40
1.2
6
500
1.2
160
Max
4.111
5.1
Unit
V
ppm/°C
ppm/V
ms
V
V
μA
V
μA
−0.3
0.9 × VIO
−1
−1
+0.1 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
Serial 14 bits, straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
V
V
2.375 2.5 2.625 V
4.75 5.0 5.25 V
1.8 2.5 2.7 V
1.0 μA
28 33
25 30
15.5 17
12 13
mW
mW
mW
mW
−40 +85 °C
Rev. 0 | Page 4 of 28

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AD7944 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7944
REF 1
REF 2
REFGND 3
REFGND 4
IN– 5
PIN 1
INDICATOR
AD7944
TOP VIEW
(Not to Scale)
15 TURBO
14 SDI
13 CNV
12 SCK
11 DVDD
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 2 REF
AI Reference Output/Input Voltage.
When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin.
When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied
voltage reference up to 5.0 V.
Decoupling is required with or without the internal reference and buffer. This pin is referred to the
REFGND pins and should be decoupled closely to the REFGND pins with a 10 μF capacitor.
3, 4 REFGND AI Reference Input Analog Ground.
5 IN−
AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense.
6 IN+
AI Analog Input. This pin is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to VREF.
7 PDREF
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DI Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When
this pin is high, the internal reference is powered down and an external reference must be used.
8 VIO
P Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface
(1.8 V, 2.5 V, or 2.7 V).
9 SDO
DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
10 DGND
P Digital Power Ground.
11 DVDD
P Digital Power. Nominally at 2.5 V.
12 SCK
DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
13 CNV
DI Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
14 SDI
DI Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows.
Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
15 TURBO
DI Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved,
and the ADC does not power down between conversions. When TURBO is low, the maximum throughput
is lower (2.0 MSPS), and the ADC powers down between conversions.
16 AVDD
P Input Analog Power. Nominally at 2.5 V.
17, 18 AGND
P Analog Power Ground.
Rev. 0 | Page 7 of 28

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