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18N120BN 데이터시트 PDF




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18N120BN 데이터시트, 핀배열, 회로
Data Sheet
HGTG18N120BN
December 2001
54A, 1200V, NPT Series N-Channel IGBT
The HGTG18N120BN is a Non-Punch Through (NPT) IGBT
design. This is a new member of the MOS gated high
voltage switching IGBT family. IGBTs combine the best
features of MOSFETs and bipolar transistors. This device
has the high input impedance of a MOSFET and the low
on-state conduction loss of a bipolar transistor.
The IGBT is ideal for many high voltage switching
applications operating at moderate frequencies where low
conduction losses are essential, such as: AC and DC motor
controls, power supplies and drivers for solenoids, relays
and contactors.
Formerly Developmental Type TA49288.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HGTG18N120BN
TO-247
G18N120BN
NOTE: When ordering, use the entire part number.
Symbol
C
Features
• 54A, 1200V, TC = 25oC
• 1200V Switching SOA Capability
• Typical Fall Time . . . . . . . . . . . . . . . . 140ns at TJ = 150oC
• Short Circuit Rating
• Low Conduction Loss
• Avalanche Rated
Temperature Compensating SABER™ Model
www.fairchildsemi.com
Packaging
JEDEC STYLE TO-247
E
C
G
G
www.DataSheet4U.com
E
FAIRCHILD SEMICONDUCTOR IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS
4,364,073
4,417,385
4,430,792
4,443,931
4,466,176
4,516,143
4,532,534
4,587,713
4,598,461
4,605,948
4,620,211
4,631,564
4,639,754
4,639,762
4,641,162
4,644,637
4,682,195
4,684,413
4,694,313
4,717,679
4,743,952
4,783,690
4,794,432
4,801,986
4,803,533
4,809,045
4,809,047
4,810,665
4,823,176
4,837,606
4,860,080
4,883,767
4,888,627
4,890,143
4,901,127
4,904,609
4,933,740
4,963,951
4,969,027
©2001 Fairchild Semiconductor Corporation
HGTG18N120BN Rev. B




18N120BN pdf, 반도체, 판매, 대치품
HGTG18N120BN
Typical Performance Curves Unless Otherwise Specified (Continued)
80
60
TC = -55oC
TC = 25oC
40
20
0
0
TC = 150oC
DUTY CYCLE < 0.5%, VGE = 12V
PULSE DURATION = 250µs
246 8
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
10
FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGE
100
TC = -55oC
80
60
TC = 25oC
TC = 150oC
40
20
0
0
DUTY CYCLE < 0.5%, VGE = 15V
PULSE DURATION = 250µs
2468
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
10
FIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE
12
RG = 3, L = 1mH, VCE = 960V
10
TJ = 150oC, VGE = 12V, VGE = 15V
8
6
4
2
TJ = 25oC, VGE = 12V, VGE = 15V
0
5 10 15 20 25 30 35 40
ICE, COLLECTOR TO EMITTER CURRENT (A)
www.DatFaISGhUeReEt4U7..cToUmRN-ON ENERGY LOSS vs COLLECTOR TO
EMITTER CURRENT
40 RG = 3, L = 1mH, VCE = 960V
35 TJ = 25oC, TJ = 150oC, VGE = 12V
30
25
20
TJ = 25oC, TJ = 150oC, VGE = 15V
15
5 10 15 20 25 30 35 40
ICE, COLLECTOR TO EMITTER CURRENT (A)
FIGURE 9. TURN-ON DELAY TIME vs COLLECTOR TO
EMITTER CURRENT
©2001 Fairchild Semiconductor Corporation
4.5
RG = 3, L = 1mH, VCE = 960V
4.0
3.5 TJ = 150oC, VGE = 12V OR 15V
3.0
2.5
2.0
1.5 TJ = 25oC, VGE = 12V OR 15V
1.0
0.5
5
10 15 20 25 30 35
ICE, COLLECTOR TO EMITTER CURRENT (A)
40
FIGURE 8. TURN-OFF ENERGY LOSS vs COLLECTOR TO
EMITTER CURRENT
120
RG = 3, L = 1mH, VCE = 960V
100 TJ = 25oC, TJ = 150oC, VGE = 12V
80
60
40
20
TJ = 25oC OR TJ = 150oC, VGE = 15V
0
5 10 15 20 25 30 35 40
ICE, COLLECTOR TO EMITTER CURRENT (A)
FIGURE 10. TURN-ON RISE TIME vs COLLECTOR TO
EMITTER CURRENT
HGTG18N120BN Rev. B

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18N120BN 전자부품, 판매, 대치품
HGTG18N120BN
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic discharge of
energy through the devices. When handling these devices,
care should be exercised to assure that the static charge
built in the handler’s body capacitance is not discharged
through the device. With proper handling and application
procedures, however, IGBTs are currently being extensively
used in production by numerous equipment manufacturers in
military, industrial and consumer applications, with virtually
no damage problems due to electrostatic discharge. IGBTs
can be handled safely if the following basic precautions are
taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as “ECCOSORBD™ LD26” or equivalent.
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5. Gate Voltage Rating - Never exceed the gate-voltage
rating of VGEM. Exceeding the rated VGE can result in
permanent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are
essentially capacitors. Circuits that leave the gate
open-circuited or floating should be avoided. These
conditions can result in turn-on of the device due to
voltage buildup on the input capacitor due to leakage
currents or pickup.
7. Gate Protection - These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate
www.DatapSrhoeteetc4tUio.ncoismrequired an external Zener is recommended.
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
frequency vs collector current (ICE) plots are possible using
the information shown for a typical unit in Figures 5, 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows fMAX1 or fMAX2; whichever is smaller at each
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I).
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
are possible. td(OFF)I and td(ON)I are defined in Figure 19.
Device turn-off delay can establish an additional frequency
limiting condition for an application other than TJM. td(OFF)I
is important when controlling output ripple under a lightly
loaded condition.
fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON2). The
allowable dissipation (PD) is defined by PD = (TJM - TC)/RθJC.
The sum of device switching and conduction losses must
not exceed PD . A 50% duty factor was used (Figure 3) and
the conduction losses (PC) are approximated by
PC = (VCE x ICE)/2.
EON2 and EOFF are defined in the switching waveforms
shown in Figure 19. EON2 is the integral of the
instantaneous power loss (ICE x VCE) during turn-on and
EOFF is the integral of the instantaneous power loss
(ICE x VCE) during turn-off. All tail losses are included in
the calculation for EOFF; i.e., the collector current equals
zero (ICE = 0).
©2001 Fairchild Semiconductor Corporation
HGTG18N120BN Rev. B

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