Datasheet.kr   

28F640L18 데이터시트 PDF




Intel Corporation에서 제조한 전자 부품 28F640L18은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 28F640L18 자료 제공

부품번호 28F640L18 기능
기능 (28FxxxL18) StrataFlash Wireless Memory
제조업체 Intel Corporation
로고 Intel Corporation 로고


28F640L18 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 30 페이지수

미리보기를 사용할 수 없습니다

28F640L18 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V low-power buffered programming at
7 µs/byte (Typ)
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
— Multiple 16-Mbit partitions: 256-Mbit devices
— Four 16-Kword parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status Register for partition and device status
Power
— VCC (core) = 1.7 V - 2.0 V
— VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 30 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 15 mA (Typ)
at 54 MHz
— Automatic Power Savings mode
Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
Density and Packaging
— 64-, 128-, and 256-Mbit density in VF BGA
packages
— 128/0 and 256/0 density in SCSP
— 16-bit wide data bus
The Intel StrataFlash® wireless memory (L18) device is the latest generation of Intel
StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-
standard chip scale packaging.
Order Number: 251902, Revision: 009
April 2005




28F640L18 pdf, 반도체, 판매, 대치품
Intel StrataFlash® Wireless Memory (L18)
9.1.4 Standby.................................................................................................................. 46
9.1.5 Reset ..................................................................................................................... 46
9.2 Device Commands ............................................................................................................. 47
9.3 Command Definitions ......................................................................................................... 48
10.0 Read Operations .................................................................................................................... 50
10.1
10.2
10.3
Asynchronous Page-Mode Read........................................................................................ 50
Synchronous Burst-Mode Read.......................................................................................... 50
10.2.1 Burst Suspend ....................................................................................................... 51
Read Configuration Register (RCR) ................................................................................... 51
10.3.1 Read Mode ............................................................................................................ 52
10.3.2 Latency Count........................................................................................................ 52
10.3.3 WAIT Polarity......................................................................................................... 54
10.3.3.1 WAIT Signal Function ............................................................................ 54
10.3.4 Data Hold............................................................................................................... 55
10.3.5 WAIT Delay............................................................................................................ 56
10.3.6 Burst Sequence ..................................................................................................... 56
10.3.7 Clock Edge ............................................................................................................ 57
10.3.8 Burst Wrap............................................................................................................. 57
10.3.9 Burst Length .......................................................................................................... 57
11.0 Programming Operations .................................................................................................. 58
11.1
11.2
11.3
11.4
11.5
www.DataSheet4U.c1o1m.6
Word Programming............................................................................................................. 58
11.1.1 Factory Word Programming................................................................................... 59
Buffered Programming........................................................................................................ 59
Buffered Enhanced Factory Programming ......................................................................... 60
11.3.1 Buffered EFP Requirements and Considerations.................................................. 60
11.3.2 Buffered EFP Setup Phase.................................................................................... 61
11.3.3 Buffered EFP Program/Verify Phase ..................................................................... 61
11.3.4 Buffered EFP Exit Phase ....................................................................................... 62
Program Suspend............................................................................................................... 62
Program Resume................................................................................................................ 63
Program Protection............................................................................................................. 63
12.0 Erase Operations................................................................................................................... 64
12.1 Block Erase......................................................................................................................... 64
12.2 Erase Suspend ................................................................................................................... 64
12.3 Erase Resume .................................................................................................................... 65
12.4 Erase Protection ................................................................................................................. 65
13.0 Security Modes....................................................................................................................... 66
13.1
13.2
Block Locking...................................................................................................................... 66
13.1.1 Lock Block ............................................................................................................. 66
13.1.2 Unlock Block .......................................................................................................... 66
13.1.3 Lock-Down Block ................................................................................................... 66
13.1.4 Block Lock Status .................................................................................................. 67
13.1.5 Block Locking During Suspend.............................................................................. 67
Protection Registers ........................................................................................................... 68
13.2.1 Reading the Protection Registers .......................................................................... 69
13.2.2 Programming the Protection Registers.................................................................. 70
13.2.3 Locking the Protection Registers ........................................................................... 70
April 2005
4
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet

4페이지










28F640L18 전자부품, 판매, 대치품
Intel StrataFlash® Wireless Memory (L18)
09/02/04
09/29/04
04/22/05
-007
-008
-009
Added Table 7 “Bus Operations Summary” on page 45
Modified Table 32 “L18 SCSP Package Ordering Information” on page 105 and added the following
order items:
* RD48F2000L0YTQ0, RD48F2000L0YBQ0
* RD48F4000L0YTQ0, RD48F4000L0YBQ0
* PF48F3000L0YTQ0, PF48F3000L0YBQ0
* PF48F4000L0YTQ0, PF48F4000L0YBQ0
* NZ48F4000L0YTQ0, NZ48F4000L0YBQ0
* JZ48F4000LOYTQ0, JZ48F4000LOYBQ0
Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm
Added mechanical drawing Figure 4 “256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimen-
sions (8x11x1.0 mm)” on page 15
In Table 32 “L18 SCSP Package Ordering Information” on page 105, corrected 256L18 package
size from 8x10x1.2 mm to 8x11x1.2 mm
Removed Bin 2 LC and Frequency Support Tables
Added back VF BGA mechanical drawings
Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP
Updated Ordering Info
Minor text edits
Converted datasheet to new template
In Table 4 “Bottom Parameter Memory Map” on page 24, corrected 256-Mbit Blk 131 address
range from 100000 - 10FFFF to 800000 - 80FFFF
In Section 5.1, “Absolute Maximum Ratings” on page 25, corrected Voltage on any signal (except
VCC, VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V
In Section E.2, “Ordering Information for SCSP” on page 105, corrected package designators for
leaded and lead-free packages from RD/PF to NZ/JZ
www.DataSheet4U.com
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
7

7페이지


구       성 총 30 페이지수
다운로드[ 28F640L18.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
28F640L18

(28FxxxL18) StrataFlash Wireless Memory

Intel Corporation
Intel Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵