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부품번호 | NBXSPA008 기능 |
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기능 | LVDS Clock Oscillator | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 6 페이지수
NBXSPA008
2.5 V / 3.3 V, 161.1328 MHz
LVDS Clock Oscillator
The NBXSPA008 single frequency crystal oscillator (XO) is
designed to meet today’s requirements for 2.5 V and 3.3 V LVDS
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide
161.1328 MHz, ultra low jitter and phase noise LVDS differential
output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
• LVDS Differential Output
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz)
• Output Frequency − 161.1328 MHz
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
• Operating Range: 2.5 V ±5%
Operating Range: 3.3 V ±10%
• Total Frequency Stability − $50 ppm
• This is a Pb−Free Device
Applications
• Ethernet, Gigabit Ethernet
• WAN
• Networking
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VDD
6
CLK CLK
54
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MARKING DIAGRAM
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXSPA008
161.1328
AWLYYWW
NBXSPA008
161.1328
A
WL
YY
WW
G or G
= NBXSPA008 (±50 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NBXSPA008LN1TAG CLCC−6
1000/
(Pb−Free) Tape & Reel
NBXSPA008LNHTAG CLCC−6
100/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1 23
OE NC GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 0
1
Publication Order Number:
NBXSPA008/D
NBXSPA008
Table 6. AC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 4)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
fCLKOUT
Df
FNOISE
Output Clock Frequency
Frequency Stability − NBXSPA008
Phase−Noise Performance
fCLKout = 161.1328 MHz
(See Figures 3 and NO TAG)
(Note 5)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
161.1328
−101
−119
−126
MHz
±50 ppm
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz of Carrier
−127
dBc/Hz
1 MHz of Carrier
−135
dBc/Hz
10 MHz of Carrier
−159
dBc/Hz
tjit(F)
tjitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
0.5 0.75 ps
1 8 ps
7 35 ps
Period, RMS
10,000 Cycles
0.6 4 ps
Period, Peak−to−Peak
10,000 Cycles
5 20 ps
tOE/OD
tDUTY_CYCLE
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
200 ns
48 50 52 %
tR Output Rise Time (20% and 80%)
115 400 ps
tF Output Fall Time (80% and 20%)
115 400 ps
tstart Start−up Time
Aging
1st Year
1 5 ms
3 ppm
Every Year After 1st
1 ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
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Figure 3. Typical Phase Noise Plot at 161.1328 MHz
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부품번호 | 상세설명 및 기능 | 제조사 |
NBXSPA008 | LVDS Clock Oscillator | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |