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ISPMACH4000B 데이터시트 PDF




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부품번호 ISPMACH4000B 기능
기능 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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ISPMACH4000B 데이터시트, 핀배열, 회로
ispMACH® 4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
November 2007
Coolest Power
SuperFASTTM High Density PLDs
Data Sheet DS1020
Features
C
TM
Broad Device Offering
High Performance
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns propagation delay
• Up to four global clock pins with programmable
• Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
– Extended: -40 to 130°C junction (Tj)
• For AEC-Q100 compliant devices, refer to
clock polarity control
LA-ispMACH 4000V/Z Automotive Data Sheet
• Up to 80 PTs per output
Ease of Design
Easy System Integration
• Superior solution for power sensitive consumer
• Enhanced macrocells with individual clock,
applications
reset, preset and clock enable controls
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Up to four global OE controls
• Operation with 3.3V (4000V), 2.5V (4000B) or
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
1.8V (4000C/Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
path • Hot-socketing
• Wide input gating (36 input logic blocks) for fast
• Open-drain capability
counters, state machines and address decoders
• Input pull-up, pull-down or bus-keeper
Zero Power (ispMACH 4000Z) and Low
• Programmable output slew rate
Power (ispMACH 4000V/B/C)
• 3.3V PCI compatible
• Typical static current 10µA (4032Z)
• IEEE 1149.1 boundary scan testable
• Typical static current 1.3mA (4000C)
• 3.3V/2.5V/1.8V In-System Programmable
• 1.8V core low dynamic power
(ISP™) using IEEE 1532 compliant interface
• ispMACH 4000Z operational down to 1.6V VCC
• I/O pins with fast setup path
• Lead-free package options
Table 1. ispMACH 4000V/B/C Family Selection Guide
www.DataSheet4U.com
ispMACH
4032V/B/C
ispMACH
4064V/B/C
ispMACH
4128V/B/C
ispMACH
4256V/B/C
ispMACH
4384V/B/C
Macrocells
32 64 128 256 384
I/O + Dedicated Inputs 30+2/32+4
30+2/32+4/
64+10
64+10/92+4/ 64+10/96+14/ 128+4/192+4
96+4
128+4/160+4
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
2.5
1.8
2.2
400
3.3/2.5/1.8V
2.5
1.8
2.2
400
3.3/2.5/1.8V
2.7
1.8
2.7
333
3.3/2.5/1.8V
3.0
2.0
2.7
322
3.3/2.5/1.8V
3.5
2.0
2.7
322
3.3/2.5/1.8V
Pins/Package
44 TQFP
48 TQFP
44 TQFP
48 TQFP
100 TQFP
100 TQFP
128 TQFP
144 TQFP1
100 TQFP
144 TQFP1
176 TQFP
256 ftBGA2/
fpBGA2, 3
176 TQFP
256 ftBGA/
fpBGA3
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 ftBGA/
fpBGA3
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1020_23.0




ISPMACH4000B pdf, 반도체, 판매, 대치품
Lattice Semiconductor
Figure 2. Generic Logic Block
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
36 Inputs
from GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
To
Product Term
Output Enable
Sharing
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
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ISPMACH4000B 전자부품, 판매, 대치품
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Table 5. Product Term Expansion Capability
Expansion
Chains
Chain-0
Chain-1
Chain-2
Chain-3
Macrocells Associated with Expansion Chain
(with Wrap Around)
M0 M4 M8 M12 M0
M1 M5 M9 M13 M1
M2 M6 M10 M14 M2
M3 M7 M11 M15 M3
Max PT/
Macrocell
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
www.DataSheet4U.com
From Logic Allocator
Delay
RP
D/T/L Q
From I/O Cell
To ORP
To GRP
CE
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
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