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ISPMACH4000ZE 데이터시트 PDF




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부품번호 ISPMACH4000ZE 기능
기능 1.8V In-System Programmable Ultra Low Power PLDs
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ISPMACH4000ZE 데이터시트, 핀배열, 회로
ispMACH® 4000ZE Family
August 2008
1.8V In-System Programmable
Ultra Low Power PLDs
Data Sheet DS1022
Features
High Performance
• fMAX = 260MHz maximum operating frequency
• tPD = 4.4ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V VCC
• Superior solution for power sensitive consumer
applications
• Per pin pull-up, pull-down or bus keeper
control*
Power Guard with multiple enable signals*
Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
• Space-saving packages
Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using
Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
On-chip user oscillator and timer*
www.DataSheet4U.com
Table 1. ispMACH 4000ZE Family Selection Guide
*New enhanced features over original ispMACH 4000Z
ispMACH 4032ZE
Macrocells
32
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
4.4
2.2
3.0
260
1.8V
Packages1 (I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
32+4
64-Ball csBGA (5 x 5mm)
32+4
100-Pin TQFP (14 x 14mm)
144-Pin TQFP (20 x 20mm)
144-Ball csBGA (7 x 7mm)
1. Pb-free only.
ispMACH 4064ZE
64
4.7
2.5
3.2
241
1.8V
32+4
48+4
64+10
64+10
ispMACH 4128ZE
128
5.8
2.9
3.8
200
1.8V
64+10
96+4
96+4
ispMACH 4256ZE
256
5.8
2.9
3.8
200
1.8V
64+10
96+14
108+4
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1022_01.2




ISPMACH4000ZE pdf, 반도체, 판매, 대치품
Lattice Semiconductor
Figure 3. AND Array
In[0]
In[34]
In[35]
ispMACH 4000ZE Family Data Sheet
PT0
PT1
PT2 Cluster 0
PT3
PT4
Note:
Indicates programmable fuse.
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE/BIE
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product
terms. The software automatically considers the availability and distribution of product term clusters as it fits the
functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and
an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased perfor-
mance.
The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
www.DataSheet4WUi.dcoemSteering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
n
Cluster
Individual Product
Term Allocator
5-PT
From
n-4
1-80
PTs
To XOR (MC)
to from from
n+1 n+2 n+1
Cluster
Allocator
4
To n+4
SuperWIDE™
Steering Logic

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ISPMACH4000ZE 전자부품, 판매, 대치품
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The ispMACH 4000ZE family architecture accommodates both block-level and macrocell-level set and reset capa-
bility. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macro-
cell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset
functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, pro-
viding flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000ZE device has up to four clock pins that are also routed to the GRP to be used as inputs.
These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock sig-
www.DantaalSshteheat4tUc.caonmbe used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations
of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
Block CLK0
CLK1
Block CLK1
CLK2
CLK3
Block CLK2
Block CLK3
7

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