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ADP5587 데이터시트 PDF




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부품번호 ADP5587 기능
기능 Mobile I/O Expander And QWERTY Keypad Controller
제조업체 Analog Devices
로고 Analog Devices 로고


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ADP5587 데이터시트, 핀배열, 회로
FEATURES
18-GPIO port expander or 10 × 8 keypad matrix
GPIOs configurable as GPIs, GPOs, and keypad rows or
columns
I2C interface with auto-increment
1.7 V to 3.6 V operation
Keypad lock capability
Open-drain interrupt output
Key press and key release interrupts
GPI interrupt with level programmability
Programmable pull-ups
Key event counter with overflow interrupt
275 μs debounce on the reset line and GPIs
1 μA typical idle current
55 μA typical polling current
Small 4 mm × 4 mm LFCSP package
APPLICATIONS
Keypad and I/O expander designed for QWERTY type phones
that require a large keypad matrix
GENERAL DESCRIPTION
The ADP5587 is an I/O port expander and keypad matrix
designed for QWERTY type phones that require a large keypad
matrix and expanded I/O lines. I/O expander ICs are used in
mobile platforms as a solution to the limited number of GPIOs
available in the main processor.
In its small 4 mm × 4 mm package, the ADP5587 contains
www.DaentaoSuhgehetp4oUw.ceormto handle all key-scanning and decoding and
to flag the processor of key presses and releases via the I2C
interface and interrupt. The ADP5587 frees the main micro-
processor from the need to monitor the keypad, thereby
minimizing current drain and increasing processor bandwidth.
The ADP5587 is also equipped with a buffer/FIFO and key
event counter to handle and keep track of up to 10 unprocessed
key or GPI events with overflow wrap and interrupt capability.
Mobile I/O Expander and
QWERTY Keypad Controller
ADP5587
FUNCTIONAL BLOCK DIAGRAM
ADP5587
GND 19
VCC 21
SCL 23
SDA 22
RST 20
INT 24
CONTROL
REGISTERS
CONTROL
INTERFACE
C9
18
C8
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 1.
The ADP5587 has keypad lock capability with an option to
trigger or not trigger an interrupt at key presses and releases.
All communication to the main processor is done using one
interrupt line and two I2C-compatible interface lines. The
ADP5587 can be configured as a keypad matrix of up to 8 rows ×
10 columns (a maximum of 80 keys).
When the ADP5587 is used for smaller keypad matrices, unused
row and column pins can be reconfigured to act as general-
purpose inputs or outputs. R0 to R7 denote the row pins of the
matrix, whereas C0 to C9 denote the column pins. At power-up,
all rows and columns default to GPIs and must be programmed
to function as part of the keypad matrix or as GPOs.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.




ADP5587 pdf, 반도체, 판매, 대치품
ADP5587
AC CHARACTERISTICS
Table 4. General AC Characteristics1
Parameter
Delay from Reset Deassertion to I2C Access
Keypad Unlock Timer
Keypad Interrupt Mask Timer
Debounce
1 Guaranteed by design.
Table 5. I2C AC Electrical Characteristics1
Parameter
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time for Stop and Start
Setup Time for Stop Condition
Rise Time for SCL and SDA2
Fall Time for SCL and SDA2
Pulse Width of Suppressed Spike
1 Guaranteed by design.
2 tR and tF are measured between 0.3 × VCC and 0.7 × VCC.
Symbol
RSTD
TKUT
TKIMT
TD
Min
60
Typ Max Unit
μs
7 sec
31 sec
275 μs
Symbol
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1 CB
20 + 0.1 CB
0
Typ
Max Unit
400 kHz
μs
μs
ns
0.9 μs
μs
μs
μs
μs
300 ns
300 ns
50 μs
SDA
tLOW
tR tSU, DAT
tF tF
tHD, STA
www.DataSheSeCt4LU.com
S tHD, DAT
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
tHIGH
tSU, STA
Sr
Figure 2. I2C Interface Timing Diagram
tSP tR
tBUF
tSU, STO
P
S
Rev. 0 | Page 4 of 24

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ADP5587 전자부품, 판매, 대치품
THEORY OF OPERATION
VCC
GND
19
VCC
21
SCL
23
SDA
22
RST
20
CONTROL
REGISTERS
INT
24
ADP5587
CONTROL
INTERFACE
C9
18
C8
17
SCL
SDA
RST
INT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A7 A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
E7 E6 E5 E4 E3 E2 E1 E0
F7 F6 F5 F4 F3 F2 F1 F0
G7 G6 G5 G4 G3 G2 G1 G0
H7 H6 H5 H4 H3 H2 H1 H0
I7 I6 I5 I4 I3 I2 I1 I0
J7 J6 J5 J4 J3 J2 J1 J0
Figure 4. Typical Operating Circuit
ADP5587
The ADP5587 is a GPIO expander that can be configured either
as an 18 I/O port expander or as a 10 column × 8 row keypad
matrix (80 keys maximum). It is ideal for cellular phone designs
and other portable devices that require a large extended keypad
and/or expanded I/Os. When smaller size keypads are required,
www.DauantnaduSsGheedPeIGts4)PU. IA.cOollsmGinPtIhOesk(eryopwasdamndatcroixlucmannsb)eduesfaeudltatsoIG/OPsIs(GatPOs
power-up with pull-ups and debounce enabled.
KEYPAD OPERATION
Any number of rows and columns, up to 10 columns × 8 rows,
can be configured to be part of the keypad matrix. The rows and
columns that make up the keypad matrix must be configured by
setting the corresponding bits in Register 0x1D to Register 0x1F.
Key presses and releases appear in the key event table/registers
with a decimal value of 1 (0x01 hexadecimal or 0000001 binary)
through a decimal value of 80 (0x50 hexadecimal or 1010000
binary). See Table 9 for key event number assignments. The
keypad, in idle mode, is configured with columns driven low
and rows as inputs configured high with pull-up resistors.
Table 9. Key Event Number Assignment Table
Row C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
R0 1 2 3 4 5 6 7 8 9 10
R1 11 12 13 14 15 16 17 18 19 20
R2 21 22 23 24 25 26 27 28 29 30
R3 31 32 33 34 35 36 37 38 39 40
R4 41 42 43 44 45 46 47 48 49 50
R5 51 52 53 54 55 56 57 58 59 60
R6 61 62 63 64 65 66 67 68 69 70
R7 71 72 73 74 75 76 77 78 79 80
When one key press or multiple key presses (short between
column and row) occur, the internal state machine checks the
row pins to determine which one is driven low and then triggers
an internal interrupt. The state machine then starts a key scan
cycle to determine which columns are involved in the key press.
After a key has been pressed for 25 ms, the state machine sets
the appropriate key number in the key event status register with
the key-pressed bits set (the MSB in the key event register) in
the order detected. The state machine then sets the KE_INT bit
in Register 0x02. If the KE_IEN field in Register 0x01 is set, an
interrupt is sent to the host processor.
Rev. 0 | Page 7 of 24

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