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PDF LMZ12003 Data sheet ( Hoja de datos )
| Número de pieza | LMZ12003 | |
| Descripción | Power Module | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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DataSheet.in
LMZ12003
April 12, 2010
3A SIMPLE SWITCHER® Power Module with 20V Maximum
Input Voltage
Easy to use 7 pin package
Performance Benefits
■ Operates at high ambient temperature with no thermal
derating
■ High efficiency reduces system heat generation
■ Low radiated emissions (EMI) complies with EN55022
class B standard
■ Passes 10V/m radiated immunity EMI test standard
EN61000 4-3
TO-PMOD 7 Pin Package
30109086
10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in)
θJA = 20°C/W, θJC = 1.9°C/W
RoHS Compliant
System Performance
Efficiency VIN = 12V VOUT = 5.0V
Electrical Specifications
■ 18W maximum total power output
■ Up to 3A output current
■ Input voltage range 4.5V to 20V
■ Output voltage range 0.8V to 6V
■ Efficiency up to 92%
Key Features
■ Integrated shielded inductor
■ Simple PCB layout
■ Flexible startup sequencing using external soft-start
capacitor and precision enable
■ Protection against inrush currents and faults such as input
UVLO and output short circuit
■ -40°C to 125°C junction temperature range
■ Single exposed pad and standard pinout for easy
mounting and manufacturing
■ Fast transient response for FPGAs and ASICs
■ Low output voltage ripple
■ Pin-to-pin compatible family:
LMZ14203/2/1 (42V max 3A, 2A, 1A)
LMZ12003/2/1 (20V max 3A, 2A, 1A)
■ Fully Webench® Power Designer enabled
Applications
■ Point of load conversions from 5V and 12V input rail
■ Time critical projects
■ Space constrained high thermal requirement applications
■ Negative output voltage applications (See AN-2027)
30109018
Thermal derating curve
VIN = 12V VOUT = 5.0V
30109019
Radiated Emissions (EN 55022 Class B)
from Evaluation Board
© 2010 National Semiconductor Corporation 301090
30109050
www.national.com
1 page  
DataSheet.in
Symbol Parameter
η Efficiency
η Efficiency
Conditions
VIN = 12V VO = 1.8V IO = 1A
VIN = 12V VO = 1.8V IO = 3A
Min
(Note 3)
Typ
(Note 4)
87
77
Max
(Note 3)
Units
%
%
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
Note 5: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.
Note 6: Theta JA measured on a 1.705” x 3.0” four layer board, with one ounce copper, thirty five 12 mil thermal vias, no air flow, and 1W power dissipation.
Refer to PCB layout diagrams
Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic; Tam-
bient = 25 C for efficiency curves and waveforms.
Efficiency 6V Input @ 25°C
Dissipation 6V Input @ 25°C
30109021
Efficiency 12V Input @ 25°C
30109022
Dissipation 12V Input @ 25°C
30109003
5
30109004
www.national.com
5 Page 
DataSheet.in
should be routed away from the body of the LMZ12003 to
minimize noise.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
ground planes. For best results use a 6 x 6 via array with
minimum via diameter of 10mils (254 μm) thermal vias spaced
59mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference.
If FB rises above 0.92V the on-time is immediately terminat-
ed. This condition is known as over-voltage protection (OVP).
It can occur if the input voltage is increased very suddenly or
if the output load is decreased very suddenly. Once OVP is
activated, the top MOSFET on-times will be inhibited until the
condition clears. Additionally, the synchronous MOSFET will
remain on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by
monitoring the current in the synchronous MOSFET. Refer-
ring to the Functional Block Diagram, when the top MOSFET
is turned off, the inductor current flows through the load, the
PGND pin and the internal synchronous MOSFET. If this cur-
rent exceeds 4.2A (typical) the current limit comparator dis-
ables the start of the next on-time period. The next switching
cycle will occur only if the FB input is less than 0.8V and the
inductor current has decreased below 4.2A. Inductor current
is monitored during the period of time the synchronous MOS-
FET is conducting. So long as inductor current exceeds 4.2A,
further on-time intervals for the top MOSFET will not occur.
Switching frequency is lower during current limit due to the
longer off-time. It should also be noted that current limit is
dependent on both duty cycle and temperature as illustrated
in the graphs in the typical performance section.
THERMAL PROTECTION
The junction temperature of the LMZ12003 should not be al-
lowed to exceed its maximum ratings. Thermal protection is
implemented by an internal Thermal Shutdown circuit which
activates at 165 °C (typ) causing the device to enter a low
power standby state. In this state the main MOSFET remains
off causing VO to fall, and additionally the CSS capacitor is
discharged to ground. Thermal protection helps prevent
catastrophic failures for accidental device overheating. When
the junction temperature falls back below 145 °C (typ Hyst =
20 °C) the SS pin is released, VO rises smoothly, and normal
operation resumes.
Applications requiring maximum output current especially
those at high input voltage may require application derating
at elevated temperatures.
ZERO COIL CURRENT DETECTION
The current of the lower (synchronous) MOSFET is monitored
by a zero coil current detection circuit which inhibits the syn-
chronous MOSFET when its current reaches zero until the
next on-time. This circuit enables the DCM operating mode,
which improves efficiency at light loads.
PRE-BIASED STARTUP
The LMZ12003 will properly start up into a pre-biased output.
This startup situation is common in multiple rail logic applica-
tions where current paths may exist between different power
rails during the startup sequence. The following scope cap-
ture shows proper behavior during this event.
Pre-Biased Startup
30109025
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LMZ12003.PDF ] | |
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