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ADP2116 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ADP2116
기능 Step-Down DC-to-DC Regulator
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ADP2116 데이터시트, 핀배열, 회로
Configurable, Dual 3 A/Single 6 A,
Synchronous, Step-Down DC-to-DC Regulator
ADP2116
FEATURES
Configurable 3 A/3 A or 3 A/2 A dual-output load
combinations or 6 A combined single-output load
High efficiency: up to 95%
Input voltage, VIN: 2.75 V to 5.5 V
Selectable fixed output voltage of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,
or 3.3 V, or adjustable output voltage to 0.6 V minimum
±1.5% accurate reference voltage
Selectable switching frequency of 300 kHz, 600 kHz, 1.2 MHz,
or synchronized from 200 kHz to 2 MHz
Optimized gate slew rate for reduced EMI
External synchronization input or internal clock output
Dual-phase, 180° phase-shifted PWM channels
Current mode for fast transient response
Pulse skip mode with light loads or forced PWM operation
Input undervoltage lockout (UVLO)
Independent enable inputs and power-good outputs
Overcurrent and thermal overload protection
Programmable soft start
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Point-of-load regulation
Telecommunications and networking systems
Consumer electronics
Industrial and instrumentation
Medical
GENERAL DESCRIPTION
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The ADP2116 is a versatile, synchronous, step-down switching
regulator that satisfies a wide range of customer point-of-load
requirements. The two PWM channels can be configured to deliver
independent outputs at 3 A and 3 A (or at 3 A and 2 A) or can be
configured as a single interleaved output capable of delivering 6 A.
The two PWM channels are 180° phase shifted to reduce input
ripple current and input capacitance.
The ADP2116 provides high efficiency and can operate at
switching frequencies of up to 2 MHz. At light loads, the ADP2116
can be set to operate in pulse skip mode for higher efficiency or
in forced PWM mode for noise sensitive applications.
The ADP2116 is designed with an optimized slew rate to reduce
EMI emissions, allowing the device to power sensitive, high perfor-
mance signal chain circuits. The switching frequency can be set
to 300 kHz, 600 kHz, or 1.2 MHz, or it can be synchronized to an
external clock that minimizes the system noise. The bidirectional
TYPICAL APPLICATION CIRCUIT
VIN = 5V
100k
PGOOD2
VOUT2 = 1.2V, 3A
47µF 100µF
22µF
2.2µH
SYNC
4.7k
30k10nF
820pF
10
1µF
EN2 EN1
VIN4
VIN1
VIN5
VIN2
VIN6
VIN3
PGOOD2
PGOOD1
SW1
SW3 ADP2116 SW2
SW4
PGND1
PGND3
PGND2
PGND4
FB1
FB2
V2SET
V1SET
SYNC/CLKOUT COMP1
COMP2
SS1
SS2
100k
22µF
3.3µH
PGOOD1
VOUT1 = 2.5V, 3A
47µF 22µF
27k
10nF 30k
820pF
8.2k
fSW = 600kHz
Figure 1.
100
VIN = 5.0V; VOUT = 2.5V
95 VIN = 5.0V; VOUT = 3.3V
90
85
80
75
70 VIN = 3.3V; VOUT = 1.2V
65
60
10
100 1k
LOAD CURRENT (mA)
fSW = 600kHz
10k
Figure 2. Typical Efficiency vs. Load Current
synchronization pin is also configurable as a 90° out-of-phase
output clock, providing the possibility for a stackable
multiphase power solution.
The ADP2116 input voltage range is from 2.75 V to 5.5 V and can
convert to a fixed output of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V
that can be set independently for each channel using external
resistors. If a resistor divider is used, the output voltage can be
set as low as 0.6 V. The ADP2116 operates over the −40°C to
+125°C junction temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.




ADP2116 pdf, 반도체, 판매, 대치품
ADP2116
Parameter
SYNC Pin Capacitance to GND
SYNC Input Logic Low
SYNC Input Logic High
Phase Shift Between Channels
CLKOUT Frequency
CLKOUT Positive Pulse Time
CLKOUT Rise or Fall Time
CURRENT LIMIT
Peak Output Current Limit, Channel 1
Symbol
CSYNC
VIL_SYNC
VIH_SYNC
fCLKOUT
tCLKOUT
ILIMIT1
Conditions
fCLKOUT = 2 × fSW
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
CCLKOUT = 20 pF
All current-limit parameters provided for
VDD = VINx = 2.75 V to 5.5 V
OPCFG tied to VDD or via 82 kΩ to GND
Peak Output Current Limit, Channel 2
ILIMIT2
Current-Sense Amplifier Gain
Hiccup Time
Number of Cumulative Current-Limit
Cycles to Go into Hiccup Mode
SWITCH NODE CHARACTERISTICS
High-Side, P-Channel RDSON1
GCS
Low-Side, N-Channel RDSON1
SWx Minimum On Time
SWx Minimum Off Time
SWON MIN
SWOFF MIN
SWx Maximum Leakage Current
ENABLE INPUTS
EN1, EN2 Logic Low Level
wwwE.DNa1t,aESNh2eeLto4gUi.ccHomigh Level
EN1, EN2 Input Leakage Current
ENLO
ENHI
IEN_LEAK
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
SOFT START
SS1, SS2 Pin Current
Soft Start Threshold Voltage
Soft Start Pull-Down Current
POWER GOOD
TTMSD
ISS1, ISS2
VSS_THRESH
Overvoltage PGOODx Rising Threshold2
Overvoltage PGOODx Falling Threshold2
Undervoltage PGOODx Rising Threshold2
Undervoltage PGOODx Falling Threshold2
PGOODx Delay
PGOODx Leakage Current
PGOODx Low Saturation Voltage
OPCFG tied to VDD or via 82 kΩ to GND
OPCFG via 47 kΩ or 27 kΩ to GND
fSW = 300 kHz
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 5.5 V
VDD = VINx = 2.75 V
VDD = VINx = 2.75 V to 5.5 V, ENx = GND,
TJ = −40°C to +115°C
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = ENx = 2.75 V to 5.5 V,
TJ = −40°C to +115°C
VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V, EN = GND
All power-good parameters provided for
VDD = VINx = 2.75 V to 5.5 V
VPGOODx = VDD
IPGOODx = 1 mA
1 Pin-to-pin measurements.
2 The thresholds are expressed as a percentage of the nominal output voltage.
Rev. 0 | Page 4 of 36
Min Typ Max Unit
5 pF
0.8 V
2.0 V
180 Degrees
510
1020
2040
100
600
1200
2400
10
690
1380
2760
kHz
kHz
kHz
ns
ns
3.5 4.5 5.3 A
3.5 4.5 5.3 A
2.4 3.3 4.0 A
4 A/V
10 13.6 17 ms
8 Cycles
68
52
32
27
107
192
255
0.1 15
ns
ns
ns
μA
0.8 V
2.0 V
0.1 1
μA
150 °C
25 °C
4.8 6.0 7.8 μA
0.65 V
0.5 mA
116 %
100 108 114 %
85 92 97 %
84 %
50 μs
0.1 1
μA
50 110 mV

4페이지










ADP2116 전자부품, 판매, 대치품
ADP2116
Pin No.
14
15
16
17
Mnemonic
VIN4
VIN5
VIN6
SW4
18 SW3
19 PGND4
20 PGND3
21 PGND2
22 PGND1
23 SW2
24 SW1
25 VIN3
26 VIN2
27 VIN1
28 EN1
29 PGOOD1
30 SS1
31 V1SET
32 FB1
EP
Description
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter; drive EN1 low to turn off the Channel 1
converter. Tie EN1 to VDD for startup with VDD. When using a multiphase configuration, connect EN1 to EN2.
Open-Drain Power-Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD1 is held low when Channel 1 is out of regulation.
Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.
Output Voltage Set Pin for Channel 1. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT1, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT1, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase
configurations, the FB1 and FB2 pins should be tied together and then connected to VOUT.
Exposed Thermal Pad. Connect the exposed thermal pad to the signal/analog ground plane.
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ADP2114

Synchronous Step-Down DC-to-DC Regulator

Analog Devices
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ADP2116

Step-Down DC-to-DC Regulator

Analog Devices
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