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ADP3211 데이터시트 PDF




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부품번호 ADP3211 기능
기능 Synchronous Buck Controller
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ADP3211 데이터시트, 핀배열, 회로
ADP3211, ADP3211A
7-Bit, Programmable,
Single-Phase, Synchronous
Buck Controller
The ADP3211 is a highly efficient, singlephase, synchronous
buck switching regulator controller. With its integrated driver, the
ADP3211 is optimized for converting the notebook battery voltage to
the supply voltage required by high performance Intel chipsets. An
internal 7bit DAC is used to read a VID code directly from the
chipset or the CPU and to set the GMCH render voltage or the CPU
core voltage to a value within the range of 0 V to 1.5 V.
The ADP3211 uses a multimode architecture. It provides
programmable switching frequency that can be optimized for
efficiency depending on the output current requirement. In addition,
the ADP3211 includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that the
core voltage is always optimally positioned for a load transient. The
ADP3211 also provides accurate and reliable current overload
protection and a delayed powergood output. The IC supports
onthefly (OTF) output voltage changes requested by the chipset.
The ADP3211 has a boot voltage of 1.1 V for IMVP6.5
applications in CPU mode. The ADP3211A has a boot voltage of
1.2 V in CPU mode.
The ADP3211 is specified over the extended commercial temperature
range of 10°C to 100°C and is available in a 32lead QFN.
Features
SingleChip Solution
Fully Compatible with the Intel® IMVP6.5t CPU and GMCH
Chipset Voltage Regulator Specifications Integrated MOSFET
Drivers
Input Voltage Range of 3.3 V to 22 V
www.DataS±he7emt4UV.cWomorstCase Differentially Sensed Core Voltage Error
Overtemperature
Automatic PowerSaving Modes Maximize Efficiency During
Light Load Operation
Soft Transient Control Reduces Inrush Current and Audio Noise
Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
Builtin PowerGood Masking Supports Voltage Identification
(VID) OTF Transients
7Bit, Digitally Programmable DAC with 0 V to 1.5 V Output
ShortCircuit Protection
Current Monitor Output Signal
This is a PbFree Device
Fully RoHS Compliant
32Lead QFN
Applications
Notebook Power Supplies for Next Generation Intel Chipsets
Intel Netbook Atom Processors
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1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM
1
xxxxxx
xxxxxx
AWLYYWW
xxx = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
GPU
ILIM
1
ADP3211
ADP3211A
(top view)
VCC
BST
DRVH
SW
PVCC
DRVL
PGND
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
April, 2009 Rev. 0
1
Publication Order Number:
ADP3211/D




ADP3211 pdf, 반도체, 판매, 대치품
ADP3211, ADP3211A
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
PWRGD
Description
PowerGood Output. Opendrain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
2
IMON
Current Monitor Output. This pin sources current proportional to the output load current. A resistor connected
to FBRTN sets the current monitor gain.
3
CLKEN
Clock Enable Output. Open drain output. The pullhigh voltage on this pin cannot be higher than VCC.
4
FBRTN
Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
5 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
6
COMP
Voltage Error Amplifier Output and Frequency Compensation Point.
7
GPU
GMCH/CPU select pin. Connect to ground when powering the CPU. Connect to 5.0 V when powering the
GMCH. When GPU is connected to ground, the boot voltage is 1.1 V for the ADP3211 and 1.2 V for the
ADP3211A. When GPU is connected to 5.0 V, there is no boot voltage.
8 ILIM Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold.
9
IREF
This pin sets the internal bias currents. A 80 kW is connected from IREF to ground.
10
RPM
RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turnon
threshold voltage.
11 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator
frequency.
12
RAMP
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets
the slope of the internal PWM stabilizing ramp.
13
LLINE
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP tied to this pin sets the load line slope.
14
CSREF
Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.
15
CSFB
Noninverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this
pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier.
16
CSCOMP
Current Sense Amplifier Output and Frequency Compensation Point.
17
GND
Analog and Digital Signal Ground.
18
PGND
LowSide Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).
19
DRVL
LowSide Gate Drive Output.
www.DataShe2e0t4U.com PVCC
21 SW
Power Supply Input/Output of LowSide Gate Driver.
Current Return For HighSide Gate Drive.
22
DRVH
HighSide Gate Drive Output.
23 BST HighSide Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the
highside MOSFET is on.
24
VCC
Power Supply Input/Output of the Controller.
25 to 31
VID6 to VID0
Voltage Identification DAC Inputs. A 7bit word (the VID Code) programs the DAC output voltage, the
reference voltage of the voltage error amplifier without a load (see the VID Code Table, Table NO TAG). In
normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.5 V
range. The input is actively pulled down.
32 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.
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ADP3211 전자부품, 판매, 대치품
ADP3211, ADP3211A
ELECTRICAL CHARACTERISTICS (VCC = PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, VVID = VDAC = 1.2 V,
TA = 10°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ Max Units
PULSE WIDTH MODULATOR Clock Oscillator
RT Voltage
PWM Clock Frequency
Range (Note 2)
VRT RT = 243 kW, VVID = 1.2 V
See also VRT(VVID) formula
fCLK Operation of interest
1.08 1.2 1.35
V
0.3 3.0 MHz
RAMP GENERATOR
RAMP Voltage
RAMP Current Range (Note 2)
VRAMP
IRAMP
EN = H, IRAMP = 60 mA
EN = L
EN = H
EN = L, RAMP = 19 V
0.9 1.0 1.1
VIN
1.0
0.5
100
+0.5
V
mA
PWM COMPARATOR
PWM Comparator Offset
(Note 2)
VOSRPM
3.0
+3.0 mV
RPM COMPARATOR
RPM Current
RPM Comparator Offset
(Note 2)
IRPM
VOSRPM
VVID = 1.2 V, RT = 243 kW
See also IRPM(RT) formula
VCOMP (1 + VRPM)
6.0
3.0
+3.0
mA
mV
SWITCH AMPLIFIER
SW Input Resistance
RSW
ZERO CURRENT SWITCHING COMPARATOR
Measured from SW to PGND
1.3 kW
SW ZCS Threshold
Masked OffTime
VZCSSW
tOFFMSKD
DCM mode, DPRSLP = 3.3 V
Measured from DRVH neg edge to DRVH
pos edge at max frequency of operation
4.0 mV
700 ns
SYSTEM I/O BUFFERS EN and VID[6:0] INPUTS
Input Voltage
Input Current
www.DataSVhIDeeDt4eUla.cyoTmime (Note 2)
VEN,VID[6:0]
IEN,VID[6:0]
Refers to driving signal level
Logic low, Isink = 1 mA
Logic high, Isource = 5 mA
VEN,VID[6:0] = 0 V
0.2 V < VEN,VID[6:0] VCC
Any VID edge to 10% of FB change
0.3
1.0
10
1.0
200
V
nA
mA
ns
GPU INPUT
Input Voltage
Input Current
VGPU
IGPU
Refers to driving signal level
Logic low, Isink = 1 mA
Logic high, Isource = 5 mA
GPU = L or GPU = H (static)
0.8 V < EN < 1.6 V (during transition)
V
0.3
4.0
10 nA
70 mA
CLKEN OUTPUT
Output Low Voltage
Output High, Leakage Current
SUPPLY
VCLKEN
ICLKEN
Logic low, ICLKEN = 4 mA
Logic high, VCLKEN = VCC
30 300 mV
3.0 mA
Supply Voltage Range
Supply Current
VCC
EN = H
EN = L
4.5 5.5 V
6.0 10 mA
60 200 mA
VCC OK Threshold
VCCOK
VCC is rising
4.4
VCC UVLO Threshold
VCCUVLO
VCC is falling
4.0 4.15
VCC Hysteresis (Note 2)
150
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
4.5
V
V
mV
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