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PDF NB7L1008M Data sheet ( Hoja de datos )
| Número de pieza | NB7L1008M | |
| Descripción | Multi-Level Inputs w/ Internal Termination | |
| Fabricantes | ON Semiconductor | |
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NB7L1008M
2.5V / 3.3V 1:8 CML Fanout
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L1008M is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008M produces eight identical output copies
of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As
such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008M
to accept various logic standards, such as LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels. The VREFAC reference output can
be used to rebias capacitor−coupled differential or single−ended input
signals. The 1:8 fanout design was optimized for low output skew
applications. The NB7L1008M is a member of the GigaComm™
family of high performance clock products.
Features
• Input Data Rate > 12 Gb/s Typical
• Data Dependent Jitter < 20 ps
• Maximum Input Clock Frequency > 8 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:8 CML Outputs, < 25 ps max
• Multi−Level Inputs, accepts LVPECL, CML, LVDS
• 160 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
www.Dat•aSDheiefft4eUre.ncotimal CML Outputs, 400 mV Peak−to−Peak, Typical
• Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
• QFN−32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
MARKING
32 DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
1008M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
IN
VT 50W
50W
IN
VREFAC
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
1 Publication Order Number:
NB7L1008M/D
1 page  
NB7L1008M
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 10)
Symbol
Characteristic
Min Typ
Max
Unit
fDATA
fINCLK
VOUTPP
VCMR
Maximum Operating Input Data Rate
Maximum Input Clock Frequency, VOUTPP w 200 mV
Output Voltage Amplitude (see Figures 2 and 5, Note 11)
fin v 4 GHz
fin v 6 GHz
Input Common Mode Range (Differential Configuration,
Note 12, Figure 9)
10
6
200
200
1050
12 Gb/s
8 GHz
mV
400
350
VCC − 50
mV
tPLH, tPHL
tPLH TC
tDC
tSKEW
Propagation Delay to Output Differential, IN/IN to Qn/Qn
Propagation Delay Temperature Coefficient −40°C to +85°C
Output Clock Duty Cycle fin v 6 GHz
Duty Cycle Skew (Note 13)
Within Device Skew (Note 14)
Device to Device Skew (Note 15)
100
45
160
35
49/51
0.15
7
25
250 ps
fs/°C
55 %
1 ps
25
70
tJITTER
Clock Jitter RMS, 1000 Cycles (Note 16) fin v 6 GHz
Data Dependent Jitter (DDJ) (Note 17) v10 Gb/s
0.2 0.8 ps
3 20
VINPP
Input Voltage Swing (Differential Configuration) (Note 18)
(Figure 5)
100
1200
mV
tr, tf Output Rise/Fall Times (20% − 80%) Qn, Qn
20 45 70 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50 W to VCC. Input
edge rates 40 ps (20% − 80%).
11. Output voltage swing is a single−ended measurement operating in differential mode.
12. VCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14. Within device skew compares coincident edges.
15. Device to device skew is measured between outputs under identical transition
16. Additive CLOCK jitter with 50% duty cycle clock signal.
17. Additive Peak−to−Peak jitter with input NRZ data at PRBS23.
18. Input voltage swing is a single−ended measurement operating in differential mode.
www.DataSheet540U0.com
450
400
350
300
250
Q Output Amplitude (mV)
.
IN
50 W
VT
50 W
IN
VCC
200
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP)
vs. Input Frequency (fin) at Ambient
Temperature (Typical)
8.0
Figure 3. Input Structure
http://onsemi.com
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