|
|
PDF NB7L11M Data sheet ( Hoja de datos )
| Número de pieza | NB7L11M | |
| Descripción | 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NB7L11M (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
NB7L11M
2.5V/3.3V Differential 1:2
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L11M is a differential 1−to−2 clock/data distribution chip
with internal source termination and CML output structure, optimized
for low skew and minimal jitter. The device is functionally equivalent to
the EP11, LVEP11, or SG11 devices. Device produces two identical
output copies of clock or data operating up to 8 GHz or 12 Gb/s,
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML output provides matching internal 50 W
terminations, and 400 mV output swings when externally terminated,
50 W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 8 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• < 0.5 ps of RMS Clock Jitter
• < 10 ps of Data Dependent Jitter
• 30 ps Typical Rise and Fall Times
www.Dat•aS1h1ee0t4pUs.cToympical Propagation Delay
• 3 ps Typical Within Device Skew
• Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output) Differential
Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
• Pb−Free Packages are Available*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
11M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our Pb−Free strategy and
soldering details, please download the ON Semicon-
ductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
VTCLK
CLK
CLK
VTCLK
50 W
50 W
Figure 1. Logic Diagram
Q0
Q0
Q1
Q1
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 1
1
Publication Order Number:
NB7L11M/D
1 page  
NB7L11M
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 9)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
VOUTPP
fdata
tPLH,
tPHL
tSKEW
Output Voltage Amplitude (@VINPPmin)
fin ≤ 6 GHz
(See Figure 3)
fin ≤ 8 GHz
Maximum Operating Data Rate
Propagation Delay to Output Differential
Duty Cycle Skew (Note 10)
Within−Device Skew
Device−to−Device Skew (Note 11)
280 400
140 300
280 400
140 300
280 400
140 300
mV
10 12
10 12
10 12
Gb/s
70 110 150 70 110 150 70 110 150 ps
2.0 5.0
3.0 15
20 50
2.0 5.0
3.0 15
20 50
2.0 5.0
3.0 15
20 50
ps
tJITTER
VINPP
RMS Random Clock Jitter (Note 12)
fin = 6 GHz
fin =8 GHz
Peak/Peak Data Dependent Jitter
fin = 2.488 Gb/s
(Note 13) fdata =5 Gb/s
fdata =10 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
0.2 0.5
0.2 0.5
2.0 5.0
3.0 8.0
5.0 10
0.2 0.5
0.2 0.5
2.0 5.0
3.0 8.0
5.0 10
0.2 0.5
0.2 0.5
2.0 5.0
3.0 8.0
5.0 10
ps
75 400 2500 75 400 2500 75 400 2500 mV
tr Output Rise/Fall Times @ 1 GHz
tf Q, Q
(20% − 80%)
30 60
30 60
30 60 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% − 80%).
10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz.
11. Device to device skew is measured between outputs under identical transition @ 1 GHz.
12. Additive RMS jitter with 50% duty cycle clock signal at 8 GHz & 10 GHz.
13. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1.
14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
www.DataSheet4U.com
500
400
300
VCC = 3.3 V
VCC = 2.5 V
200
100
0
0 1 2 3 4 5 6 7 8 9 10 11 12
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
(VINPP = 400 mV)
http://onsemi.com
5
5 Page 
NB7L11M
PACKAGE DIMENSIONS
D
ÇÇÇÇÇÇPIN 1
ÇÇÇLOCATION
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE B
A
B
E
0.15 C
0.15 C
TOP VIEW
0.10 C
16 X 0.08 C
(A3)
SIDE VIEW
A1
A
SEATING
PLANE
C
16X L
NOTE 5
D2
e
58
EXPOSED PAD
16X K
4
1
9
E2
12 e
www.DataSheet4U.com
0.10
0.05
16X b
CAB
C NOTE 3
16 13
BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.18 0.30
D 3.00 BSC
D2 1.65 1.85
E 3.00 BSC
E2 1.65 1.85
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NB7L11M/D
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet NB7L11M.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NB7L111M | 6.125Gb/s 1:10 Differential Clock/Data Driver | ON Semiconductor |
| NB7L11M | 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |