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PDF NB7VQ58M Data sheet ( Hoja de datos )
| Número de pieza | NB7VQ58M | |
| Descripción | 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7VQ58M
1.8V / 2.5V / 3.3V
Differential 2:1 Clock/Data
Multiplexer / Translator
with CML Outputs
w/ Selectable Input Equalizer
Multi−Level Inputs w/ Internal Termination
http://onsemi.com
MARKING
DIAGRAM*
16
Description
The NB7VQ58M is a high performance differential 2−to−1 Clock or
Data multiplexer with a selectable Equalizer receiver. When placed in
series with a Clock /Data path operating up to 7 GHz or 10.7 Gb/s,
respectively, the NB7VQ58M inputs will compensate the degraded
signal transmitted across an FR4 PCB backplane or cable
interconnect. Therefore, the serial data rate is increased by reducing
Inter−Symbol Interference (ISI) caused by losses in copper
interconnect or long cables.
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
1
NB7V
Q58M
ALYW G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The EQualizer ENable pin (EQEN) allows the INn/INn inputs to
either flow through or bypass the Equalizer section. Control of the
Equalizer function is realized by setting EQEN; When EQEN is set
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Low, the INn / INn inputs bypass the Equalizer. When EQEN is set
High, the INn / INn inputs flow through the Equalizer. The default
SIMPLIFIED BLOCK DIAGRAM
state at startup is LOW. As such, the NB7VQ58M is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock/Data distribution
applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ58M to accept various logic level standards, such as LVPECL,
www.DatCaSMheLeot4rUL.cVoDmS.
The NB7VQ58M produces minimal Clock or Data jitter operating
up to 7 GHz or 10.7 Gb/s, respectively.
The 16 mA differential CML outputs provide matching internal
50 W terminations and 400 mV output swings when externally
terminated with a 50 W resistor to VCC.
The NB7VQ58M is offered in a low profile 3mm x 3 mm 16−pin
VCC
EQ
QFN package and is a member of the GigaComm™ family of high
performance Clock / Data products. Application notes, models, and
support documentation are available at www.onsemi.com.
Features
• Maximum Input Data Rate > 10.7 Gb/s
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 7 GHz
• Differential CML Outputs, 400 mV Peak−to−Peak,
• Random Clock Jitter < 0.8 ps RMS
• Selectable Input Equalization
• 180 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
Typical
• Operating Range: VCC = 1.71 V to 3.6 V with GND =
0V
• Internal 50 W Input Termination Resistors
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 0
1
Publication Order Number:
NB7VQ58M/D
1 page  
NB7VQ58M
Table 7. AC CHARACTERISTICS (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 11)
Symbol
Characteristic
Min Typ Max
Unit
fMAX
fDATAMAX
fSEL
Maximum Input Clock Frequency
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
VOUTPP ≥ 200 mV
7
10.7
25
8
12
50
GHz
Gbps
MHz
VOUTPP
Output Voltage Amplitude EQEN = 0 or 1
(Note 12) (Figures 3 and 11)
fin ≤ 7 GHz 200 400
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential cross−point EQEN = 0 or 1
INn/INn to Q, Q 120 180 240
SEL to Q, Q 5
13 22
ps
ns
tPLH TC Propagation Delay Temperature Coefficient
50 Dfs/°C
tskew
Device − Device skew (tpdmax – tpdmin)
50 ps
tDC Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
fin v 5.0 GHz 45 50 55
fin v 7.0 GHz 40 50 60
%
tJITTER
RMS Random Clock Jitter (Note 13)
Peak−to−Peak Data Dependent Jitter (Note 14)
fin v 7.0 GHz
fin v 10.7 Gbps
EQEN = 0 (v 3” FR4)
EQEN = 1 (12” FR4)
0.2 0.8 ps rms
10 ps pk−pk
10
FN Phase Noise, fc = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−135
−136
−150
−151
−151
−151
dBc
t∫FN Integrated Phase Jitter (Figure 4) fc = 1 GHz, 12 kHz − 20 MHz Offset (RMS)
Crosstalk Induced Jitter (Adjacent Channel) (Note 15)
35 fs
0.7 ps RMS
VINPP
Input Voltage Swing (Differential Configuration) (Figure 11) (Note 12)
100
1200
mV
tr, tf Output Rise/Fall Times @ 1 GHz (20% − 80%)
Q, Q 15 35 50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Input and output voltage swings are single−ended measurements operating in differential mode.
www.Dat11a43S..hAAeddeddtii4ttiiUvvee.cPRomeMaSk−jittote−rPweiathk
50%
data
duty cycle clock
dependent jitter
signal.
with input
NRZ
data
at
PRBS23
at
3
Gbps.
15. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
500
450
400
350
300
250
200
0 1 2 3 4 5 6 7 8 9 10
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
−115
−120
−125
−130
−135
−140
−145
−150
−155
1.E+03
1.E+04 1.E+05 1.E+06 1.E+07
FREQUENCY OFFSET (Hz)
Figure 4. Typical Phase Noise
(VCC = 1.8 V, T = 255C, fc = 1 GHz)
1.E+08
http://onsemi.com
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