NB6LQ572M Datasheet PDF - ON Semiconductor
| Part Number | NB6LQ572M | |
| Description | 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator | |
| Manufacturers | ON Semiconductor | |
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NB6LQ572M
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 CML Clock/Data Fanout
/ Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB6LQ572M is a high performance differential 4:1 Clock /
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572M, which is pin−compatible to the
NB6LQ572M.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB6LQ572M is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when
externally loaded and terminated with a 50 W resistor to VCC and are
optimized for low skew and minimal jitter.
The NB6LQ572M is offered in a low profile 5x5mm 32−pin QFN
Pb−Free package. Application notes, models, and support
www.DatdaoSchuemet4eUnt.caotimon are available at www.onsemi.com. The NB6LQ572M
is a member of the ECLinPS MAX™ family of high performance
clock products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB6L
Q572M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Features
• Input Data Rate > 8 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:2 CML Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
• Input EQ for Backplane and Cable Interconnect
Compensation
• 150 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak,
Typical
• Operating Range: VCC = 2.375 V to 3.6 V with
GND = 0 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• 40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 0
1
Publication Order Number:
NB6LQ572M/D
|
| |
 
NB6LQ572M
Table 5. DC CHARACTERISTICS CML OUTPUT VCC = 2.375 V to 3.6 V , GND = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min Typ Max
Unit
POWER SUPPLY
VCC Power Supply Voltage
ICC Power Supply Current for VCC
(Inputs and Outputs Open)
CML OUTPUTS (Note 6)
VCC = 3.3 V
3.0
3.3
3.6 V
VCC = 2.5 V
2.375
2.5
2.625
VCC = 3.3 V
VCC = 2.5 V
130 165 mA
115 150
VOH Output HIGH Voltage
VCC = 3.3 V
VCC = 2.5 V
VCC – 30
3270
2470
VCC – 10
3290
2490
VCC
3300
2500
mV
VOL Output LOW Voltage
VCC = 3.3 V
VCC = 2.5 V
VCC – 650
2650
VCC – 650
1850
VCC – 450
2850
VCC – 450
2050
VCC – 300
3000
VCC – 300
2200
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 7 & 8) (Note 8)
VIH
VIL
Vth
VISE
VREFAC
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage (VIH – VIL)
Vth + 100
GND
1100
200
VCC
Vth – 100
VCC – 100
1200
mV
mV
mV
mV
VREF−AC Output Reference Voltage (100 mA Load)
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 & 10) (Note 9)
1050
VCC – 1250
VCC – 1050
mV
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
Differential Input Voltage (IN, IN) (VIHD – VILD)
Input Common Mode Range (Differential Configuration,
Note 10) (Figure 11)
1200
0
100
1050
VCC
VIHD – 100
1200
VCC – 50
mV
mV
mV
mV
IIH Input HIGH Current IN / INx (VTIN / VTINx Open)
IIL Input LOW Current IN / INx (VTIN / VTINx Open)
CONTROL INPUT (SELx Pin)
www.DataSheet4U.com
VIH Input HIGH Voltage for Control Pin
VIL Input LOW Voltage for Control Pin
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
−150
−150
VCC x 0.65
GND
−150
−150
150 mA
150 mA
VCC
VCC x 0.35
150
150
V
V
mA
mA
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55 W
RTOUT Internal Output Termination Resistor
45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with VCC.
6. CML outputs loaded with 50 W to VCC for proper operation.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
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Featured Datasheets
| Part Number | Description | MFRS |
| NB6LQ572 | The function is 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator. ON Semiconductor | |
| NB6LQ572M | The function is 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator. ON Semiconductor | |
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