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NB7L585 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 NB7L585은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 NB7L585 기능
기능 2.5 V / 3.3 V Differential 2:1 Mux Input To 1:6 LVPECL Clock/Data Fanout Buffer / Translator
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NB7L585 데이터시트, 핀배열, 회로
NB7L585
2.5V / 3.3V Differential 2:1
Mux Input to 1:6 LVPECL
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585 produces six identical output copies of Clock or Data
operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The NB7L585 is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585 is a member of the GigaCommfamily of high
performance clock products.
Features
Maximum Input Data Rate > 8 Gb/s
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 5 GHz
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:6 LVPECL Outputs, 20 ps max
2:1 Multi−Level Mux Inputs
175 ps Typical Propagation Delay
55 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peak−to−peak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN−32 Package, 5mm x 5mm
−40ºC to +85ºC Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
585
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
+
SEL
VREFAC0
IN0
50 W
VT0
50 W
IN0
0
Q0
Q0
Q1
Q1
Q2
IN1
50 W
VT1
50 W
IN1
VREFAC1
VCC
GND
1
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1 Publication Order Number:
NB7L585/D




NB7L585 pdf, 반도체, 판매, 대치품
NB7L585
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C
(Note 5)
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY
VCC Power Supply Voltage
VCC = 3.3V
VCC = 2.5V
3.0
2.375
3.3
2.5
3.6
2.625
V
ICC Power Supply Current (Inputs and Outputs Open)
185 225 mA
LVPECL Outputs
VOH Output HIGH Voltage (Note 6)
VCC = 3.3 V
VCC = 2.5 V
VCC – 1145
2155
1355
VOL Output LOW Voltage (Note 6)
VCC = 3.3 V
VCC = 2.5 V
VCC – 2000
1300
500
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 & 6)
VCC – 800
2500
1700
VCC – 1500
1800
1000
mV
mV
VIH Single−ended Input HIGH Voltage
VIL Single−ended Input LOW Voltage
Vth Input Threshold Reference Voltage Range (Note 8)
VISE
Single−ended Input Voltage (VIH − VIL)
VREFACx (for Capacitor− Coupled Inputs, Only)
Vth + 100
GND
1100
200
VCC
Vth − 100
VCC −100
1200
mV
mV
mV
mV
VREFAC
Output Reference Voltage @100 mA for Capacitor− Coupled
Inputs, Only
VCC – 1500 VCC – 1200 VCC – 1000
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9)
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN , IN)
Differential Input Voltage (IN , IN) (VIHD − VILD)
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1200
GND
100
1050
VCC
VIHD − 100
1200
VCC − 50
mV
mV
mV
mV
IIH Input HIGH Current IN/IN (VTIN/VTIN Open)
IIL Input LOW Current IN/IN (VTIN/VTIN Open)
CONTROL INPUT (SEL Pin)
−150
−150
150 mA
150 mA
VIH Input HIGH Voltage for Control Pin
VIL Input LOW Voltage for Control Pin
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
2.0
GND
−150
−150
VCC
mV
0.8 mV
150 mA
150 mA
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. LVPECL outputs (Qn/Qn) loaded with 50 W to VCC – 2 V for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
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NB7L585 전자부품, 판매, 대치품
NB7L585
VCC
VCC
VCC
VCC
LVPECL
Driver
Zo = 50 W
VT = VCC − 2.0 V
Zo = 50 W
NB7L585
IN
50 W
50 W
IN
CLKx
GND
GND
Figure 12. LVPECL Interface
LVDS
Driver
Zo = 50 W
VT = OPEN
Zo = 50 W
NB7L585
IN
50 W
50 W
IN
CLKx
GND
GND
Figure 13. LVDS Interface
VCC
VCC
CML
Driver
Zo = 50 W
VT = VCC
Zo = 50 W
NB7L585
IN
50 W
50 W
IN
GND
GND
Figure 14. Standard 50 W Load CML Interface
VCC
VCC
Differential
Driver
Zo = 50 W
VT = VREFAC*
Zo = 50 W
NB7L585
IN
50 W
50 W
IN
GND
GND
Figure 15. Capacitor−Coupled Differential
Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor.
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
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