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부품번호 | NB7V585M 기능 |
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기능 | 1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 8 페이지수
NB7V585M
1.8V / 2.5V Differential 2:1
Mux Input to 1:6 CML
Clock/Data Fanout
Buffer/Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7V585M is a differential 1−to−6 CML clock/data
distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50 W
termination resistors and will accept LVPECL, CML, or LVDS logic
levels (see Figure 9). The NB7V585M produces six identical output
copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively.
As such, NB7V585M is ideal for SONET, GigE, Fiber Channel,
Backplane and other clock/data distribution applications. The 16 mA
differential CML output structure provides matching internal 50 W
source terminations, 400 mV output swings when externally
terminated with a 50 W resistor to VCC (see Figure 14) and is
optimized for low skew and minimal jitter. The NB7V585M is
powered with either 1.8 V or 2.5 V supply and is offered in a low
profile 5x5 mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7V585M is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz
• Random Clock Jitter < 0.8 ps RMS, Max
www.Dat•aSLheoewt4US.kceowm 1:6 CML Outputs, 20 ps Max
• 2:1 Multi−Level Mux Inputs
• 175 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential CML Outputs, 330 mV Peak−to−Peak, Typical
• Operating Range: VCC = 1.71 V to 1.89 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM*
1 32
1
QFN32
MN SUFFIX
CASE 488AM
NB7V
585M
AWLYYWW
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
VCC
Q0
Q0
Q1
SEL Q1
VREFAC0
IN0
VT0
IN0
0
Q2
Q2
IN1
VT1
IN1
VREFAC1
VCC
GND
Q3
1 Q3
Q4
Q4
Q5
Q5
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB7V585M/D
NB7V585M
Table 5. DC CHARACTERISTICS − CML OUTPUT VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 5)
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY CURRENT
ICC Power Supply Current (Inputs and Outputs Open)
CML OUTPUTS (Note 6)
VCC = 2.65 V
VCC = 1.89 V
mA
235 260
210
VOH Output HIGH Voltage
VCC = 2.5 V
VCC = 1.8 V
VOL Output LOW Voltage
VCC = 2.5 V
VCC = 1.8 V
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figure 6)
VCC – 40
2460
1760
VCC – 500
2000
1300
VCC – 20
2480
1780
VCC – 400
2100
1400
VCC
2500
1800
VCC – 275
2200
1500
mV
mV
Vth
VIH
VIL
VISE
VREFAC
VREFAC
Input Threshold Reference Voltage Range (Note 8)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Voltage (VIH − VIL)
Output Reference Voltage @ 100 mA for Capacitor − Coupled
Inputs, Only
1050
Vth + 100
GND
200
VCC − 100
VCC
Vth − 100
1200
mV
mV
mV
mV
VCC − 625
VCC − 500
VCC − 400
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 4 and 7)
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
Differential Input Voltage (IN, IN) (VIHD − VILD)
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1100
GND
100
1050
VCC
VCC − 100
1200
VCC − 50
mV
mV
mV
mV
IIH Input HIGH Current IN/IN (VTO / VT1 Open)
IIL Input LOW Current IN/IN (VTO / VT1 Open)
CONTROL INPUT (SEL Pin)
−150
−150
150 mA
150 mA
VIH Input HIGH Voltage for Control Pin
www.DataSheet4U.com
VIL Input LOW Voltage for Control Pin
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
VCC x 0.65
VCC
mV
GND
−150
VCC x 0.35
mV
20
+150
mA
−150
5
+150
mA
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55 W
RTOUT Internal Output Termination Resistor
45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs (Qn/Qn) have internal 50 W source termination resistors and must be externally terminated with 50 W to VCCO for proper
operation.
7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
4
4페이지 NB7V585M
VCC
VCC
VCC
VCC
LVPECL
Driver
ZO = 50 W
ZOV=T =50VWCC − 2 V
NB7V585M
INx
50 W
50 W
INx
GND
GND
Figure 11. LVPECL Interface
LVDS
Driver
ZO = 50 W
ZO
=
5V0T
=
W
Open
NB7V585M
INx
50 W
50 W
INx
GND
Figure 12. LVDS Interface
GND
VCC
VCC
VCC
VCC
CML
Driver
ZO = 50 W
ZO
=
50
VT
W
=
VCC
NB7V585M
INx
50 W
50 W
INx
Differential
Driver
ZO = 50 W
ZO =VT50=WVREFAC*
NB7V585M
INx
50 W
50 W
INx
GND
GND
Figure 13. Standard 50 W Load CML Interface
www.DataSheet4U.com
GND
GND
Figure 14. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor
ORDERING INFORMATION
Device
Package
Shipping†
NB7V585MMNG
QFN32
(Pb−Free)
74 Units / Rail
NB7V585MMNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
7
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부품번호 | 상세설명 및 기능 | 제조사 |
NB7V585M | 1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |