ADP123 Datasheet PDF - Analog Devices
| Part Number | ADP123 | |
| Description | (ADP122 / ADP123) CMOS Linear Regulator | |
| Manufacturers | Analog Devices | |
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5.5 V Input, 300 mA, Low Quiescent
Current, CMOS Linear Regulator
ADP122/ADP123
FEATURES
Input voltage supply range: 2.3 V to 5.5 V
300 mA maximum output current
Fixed and adjustable output voltage versions
Very low dropout voltage: 85 mV at 300 mA load
Low quiescent current: 45 μA at no load
Low shutdown current: <1 μA
Initial accuracy: ±1% accuracy
Up to 31 fixed-output voltage options available from
1.75 V to 3.3 V
Adjustable-output voltage range
0.8 V to 5.0 V (ADP123)
Excellent PSRR performance: 60 dB at 100 kHz
Excellent load/line transient response
Optimized for small 1.0 μF ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
Compact, 5-lead TSOT package
APPLICATIONS
Digital camera and audio devices
Portable and battery-powered equipment
Automatic meter reading (AMR) meters
GPS and location management units
Medical instrumentation
Point-of-sale equipment
GENERAL DESCRIPTION
www.DaTthaeShAeDetP41U2.c2o/AmDP123 are low quiescent current, low dropout
linear regulators. They are designed to operate from an input
voltage between 2.3 V and 5.5 V and to provide up to 300 mA of
output current. The low 85 mV dropout voltage at a 300 mA load
improves efficiency and allows operation over a wide input
voltage range.
The low 170 μA of quiescent current at full load makes the ADP122
ideal for battery-operated portable equipment.
The ADP122 is capable of 31 fixed output voltages from 1.75 V
to 3.3 V. The ADP123 is the adjustable version of the device and
allows the output voltage to be set between 0.8 V and 5.0 V by
an external voltage divider.
TYPICAL APPLICATION CIRCUIT
VIN = 2.3V TO 5.5V
CIN
1µF
1 VIN VOUT 5
ADP122
2 GND
VOUT = 1.8V
COUT
1µF
ON
OFF
3 EN
NC 4
Figure 1. ADP122 with Fixed Output Voltage
VIN = 2.3V TO 5.5V
CIN
1µF
1 VIN VOUT 5
ADP123
2 GND
VOUT = 0.5V(1 + R1/R2)
COUT
1µF
R1
ON
OFF
3 EN
ADJ 4
R2
Figure 2. ADP 123 with Adjustable Output Voltage
The ADP122/ADP123 are specifically designed for stable operation
with tiny 1 μF ceramic input and output capacitors to meet the
requirements of high performance, space constrained applications.
The ADP122/ADP123 have an internal soft start that gives a
constant start-up time of 350 μs. Short-circuit protection and
thermal overload protection circuits prevent damage in adverse
conditions. The ADP122/ADP123 are available in a tiny, 5-lead
TSOT package for the smallest footprint solution to meet a
variety of portable applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to +4 V
−0.3 V to +6.5 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP122/ADP123 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ will remain within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
www.DathtaeSdheeveitc4eUi.scdomependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the
ADP122/ADP123
application and board layout. In applications in which high maxi-
mum power dissipation exists, close attention to thermal board
design is required. The value of θJA may vary, depending on PCB
material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD51-7 for detailed information on the board
construction
ΨJB is the junction-to-board thermal characterization parameter
and is measured in °C/W. The ΨJB of the package is based on
modeling and calculation using a 4-layer board. The Guidelines for
Reporting and Using Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package—factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
5-Lead TSOT
170
ΨJB
43
Unit
°C/W
ESD CAUTION
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