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PDF ATA6838 Data sheet ( Hoja de datos )
| Número de pieza | ATA6838 | |
| Descripción | Hex Half-bridge Driver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Six Half-bridge Outputs Formed by Six High-side and Six Low-side Drivers
• Capable of Switching all Kinds of Loads (Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors)
• RDSon Typically 1.0Ω at 25°C, Maximum 1.8Ω at 150°C
• Up to 1A Output Current
• Very Low Quiescent Current IS < 20 µA in Standby Mode
• Outputs Short-circuit Protected
• Overtemperature Prewarning and Protection
• Undervoltage Protection
• Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
• Serial Data Interface
• Operation Voltage up to 40V
• Daisy Chaining Possible
• Serial Interface 5V Compatible, up to 2 MHz Clock Frequency
• QFN24 Package
1. Description
The ATA6838 is a fully protected hex half-bridge driver designed in Smart Power SOI
technology, used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
Each of the six high-side and six low-side drivers is capable of driving currents up to
1A. The drivers are internally connected to form 6 half-bridges and can be controlled
separately from a standard serial data interface. Therefore, all kinds of loads, such as
bulbs, resistors, capacitors and inductors, can be combined. The IC especially sup-
ports the application of H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and
undervoltage. Various diagnosis functions and a very low quiescent current in standby
mode make a wide range of applications possible.
Automotive qualification referring to conducted interferences, EMC protection and
ESD protection gives added value and enhanced quality for the exacting requirements
of automotive applications.
www.DataSheet4U.com
Hex Half-bridge
Driver with
Serial Input
Control
ATA6838
Preliminary
4954D–AUTO–10/08
1 page  
3. Functional Description
ATA6838 [Preliminary]
www.DataSheet4U.com
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
CLK
SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF
Table 3-1. Input Data Protocol
Bit Input Register Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)
1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 LS4 See LS1
8 HS4 See HS1
9 LS5 See LS1
10 HS5 See HS1
11 LS6 See LS1
12 HS6 See HS1
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit
(shutdown delay high/low = 12 ms/1.5 ms)
Software inhibit; low = standby, high = normal operation
15 SI (data transfer is not affected by standby function because the digital
part is still powered)
4954D–AUTO–10/08
5
5 Page 
ATA6838 [Preliminary]
www.DataSheet4U.com
7. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin Symbol Min. Typ. Max. Unit Type*
5.14
Open load detection
current ratio
2, 5, 8,
11, 20,
23
IOLoutLX/
IOLoutHX
1.05
1.2
2
5.15
High-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8,
11, 20,
23
VOut1-6H
0.6
2.5 V A
5.16
Low-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8,
11, 20,
23
VOut1-6L
0.6
2 VA
5.17
5.18
5.19
5.20
5.21
High-side output switch VVS = 13V
on delay(1)
RLoad = 30Ω
Low-side output switch VVS = 13V
on delay(1)
RLoad = 30Ω
High-side output switch VVS =13V
off delay(1)
RLoad = 30Ω
Low-side output switch VVS =13V
off delay(1)
RLoad = 30Ω
Dead time between
corresponding high- and
low-side switches
VVS =13V
RLoad = 30Ω
tdon
tdon
tdoff
tdoff
tdon – tdoff
1
20 µs A
20 µs A
20 µs A
3 µs A
µs A
6 Inhibit Input
6.1
Input voltage low-level
threshold
6.2
Input voltage high-level
threshold
6.3
Hysteresis of input
voltage
VIL
0.3 ×
VVCC
VIH
ΔVI 100
0.7 ×
VVCC
700
V
V
mV
A
A
A
6.4 Pull-down current
VINH = VVCC
7 Serial Interface: Logic Inputs DI, CLK, CS
IPD 10
80 µA A
7.1
Input voltage low-level
threshold
7.2
Input voltage high-level
threshold
7.3
Hysteresis of input
voltage
VIL
0.3 ×
VVCC
VIH
ΔVI 50
0.7 ×
VVCC
500
V
V
mV
A
A
A
7.4
Pull-down current pin DI,
CLK
VDI, VCLK = VVCC
IPDSI
2
50 µA A
7.5 Pull-up current pin CS VCS= 0V
8 Serial Interface: Logic Output DO
IPUSI
–50
–2 µA A
8.1 Output voltage low level IOL = 3 mA
8.2 Output voltage high level IOL = –1 mA
VDOL
VDOH
VVCC –
0.7V
0.5 V A
VA
8.3
Leakage current
(tri-state)
VCS = VVCC,
0V < VDO < VVCC
IDO –10
+10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
µA
A
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
4954D–AUTO–10/08
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ATA6838.PDF ] | |
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