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Número de pieza | IT8510E | |
Descripción | Embedded Controller | |
Fabricantes | ITE | |
Logotipo | ||
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IT8510E/TE/G
Embedded Controller
Preliminary Specification 0.7.2
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
1 page IT8510E
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6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 54
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 54
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 54
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 55
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 55
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 55
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 55
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 55
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 56
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 56
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 56
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 56
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 57
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 57
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 57
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 57
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 58
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 58
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 58
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 58
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 58
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 59
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 59
6.2.7.9 Shared Memory Base Address High Byte Register (SHMBAH).............................. 59
6.2.7.10 Shared Memory Base Address Low Byte Register (SHMBAL) ............................... 59
6.2.7.11 Shared Memory Size Configuration Register (SHMSZ) .......................................... 60
6.2.7.12 LPC Memory Control (LPCMCTRL) ........................................................................ 60
6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 60
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 61
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 61
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 61
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 61
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 62
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 62
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 62
6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 62
6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 62
6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 63
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 63
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 63
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 63
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 63
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 64
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 64
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 64
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 64
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 64
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 65
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 65
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7.7.4.18 4.7 µs Register (4P7USREG) ................................................................................ 196
7.7.4.19 4.0 µs Register (4P0USREG) ................................................................................ 196
7.7.4.20 300 ns Register (300NSREG) ............................................................................... 196
7.7.4.21 250 ns Register (250NSREG) ............................................................................... 197
7.7.4.22 25 ms Register (25MSREG).................................................................................. 197
7.7.4.23 45.3 µs Low Register (45P3USLREG) .................................................................. 197
7.7.4.24 45.3 µs High Register (45P3USHREG)................................................................. 197
7.8 PS/2 Interface ................................................................................................................................. 198
7.8.1 Overview............................................................................................................................. 198
7.8.2 Features ............................................................................................................................. 198
7.8.3 Functional Description........................................................................................................ 198
7.8.3.1 Hardware Mode Selected ...................................................................................... 198
7.8.3.2 Software Mode Selected ....................................................................................... 199
7.8.4 EC Interface Registers ....................................................................................................... 199
7.8.4.1 PS/2 Control Register 1-4 (PSCTL1-4) ................................................................. 200
7.8.4.2 PS/2 Interrupt Control Register 1-4 (PSINT1-4)................................................... 200
7.8.4.3 PS/2 Status Register 1-4 (PSSTS1-4)................................................................... 201
7.8.4.4 PS/2 Data Register 1-4 (PSDAT1-4) ..................................................................... 201
7.9 Digital To Analog Converter (DAC)................................................................................................. 202
7.9.1 Overview............................................................................................................................. 202
7.9.2 Feature ............................................................................................................................... 202
7.9.3 Functional Description........................................................................................................ 202
7.9.4 EC Interface Registers ....................................................................................................... 202
7.9.4.1 DAC Control Register (DACCTRL)........................................................................ 202
7.9.4.2 DAC Data Channel 0~3 Register (DACDAT0~3) .................................................. 203
7.10 Analog to Digital Converter (ADC) .................................................................................................. 204
7.10.1 Overview............................................................................................................................. 204
7.10.2 Features ............................................................................................................................. 204
7.10.3 Functional Description........................................................................................................ 204
7.10.3.1 ADC General Description ...................................................................................... 205
7.10.3.2 Voltage Measurement............................................................................................ 205
7.10.3.3 ADC Operation ...................................................................................................... 206
7.10.4 EC Interface Registers ....................................................................................................... 207
7.10.4.1 ADC Status Register (ADCSTS) ........................................................................... 207
7.10.4.2 ADC Configuration Register (ADCCFG)................................................................ 208
7.10.4.3 ADC Clock Control Register (ADCCTL) ................................................................ 208
7.10.4.4 ADC Delay Control Register (ADCDCTL) ............................................................. 209
7.10.4.5 Calibration Data Control Register (KDCTL) .......................................................... 209
7.10.4.6 Voltage Channel 1 Control Register (VCH1CTL) .................................................. 210
7.10.4.7 Volt Channel 1 Data Buffer LSB (VCH1DATL)...................................................... 212
7.10.4.8 Volt Channel 1 Data Buffer MSB (VCH1DATM).................................................... 212
7.10.4.9 Voltage Channel 2 Control Register (VCH2CTL) .................................................. 212
7.10.4.10 Volt Channel 2 Data Buffer LSB (VCH2DATL)...................................................... 212
7.10.4.11 Volt Channel 2 Data Buffer MSB (VCH2DATM).................................................... 212
7.10.4.12 Voltage Channel 3 Control Register (VCHN3CTL) ............................................... 213
7.10.4.13 Volt Channel 3 Data Buffer LSB (VCH3DATL)...................................................... 213
7.10.4.14 Volt Channel 3 Data Buffer MSB (VCH3DATM).................................................... 213
7.10.4.15 Volt High Scale Calibration Data Buffer LSB (VHSCDBL) .................................... 213
7.10.4.16 Volt High Scale Calibration Data Buffer MSB (VHSCDBM) .................................. 213
7.10.4.17 Volt High Scale Gain-Error Calibration Data Buffer LSB (VHSGCDBL) ............... 214
7.10.4.18 Volt High Scale Gain-Error Calibration Data Buffer MSB (VHSGCDBM) ............. 215
7.10.5 ADC Programming Guide................................................................................................... 215
7.11 PWM and SmartAuto Fan Control (PWM) ...................................................................................... 218
7.11.1 Overview............................................................................................................................. 218
7.11.2 Features ............................................................................................................................. 218
7.11.3 Functional Description........................................................................................................ 218
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viii IT8510E/TE/G V0.7.2
11 Page |
Páginas | Total 70 Páginas | |
PDF Descargar | [ Datasheet IT8510E.PDF ] |
Número de pieza | Descripción | Fabricantes |
IT8510E | Embedded Controller | ITE |
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IT8510TE | Embedded Controller | ITE |
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