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부품번호 | KK74AC109 기능 |
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기능 | Dual J-K Flip-Flop | ||
제조업체 | KODENSHI KOREA | ||
로고 | |||
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
TECHNICAL DATA
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KK74AC109
The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109.
The device inputs are compatible with standard CMOS outputs, with
pullup resistors, they are compatible with LS/ALS outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION K
KK74AC109N Plastic
KK74AC109D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X
X X H*
H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
1
KK74AC109
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AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns)
Symbol
Parameter
VCC*
Guaranteed Limits
V 25 °C
-40°C to
85°C
Min Max Min Max
fmax Maximum Clock Frequency (Figure 1)
3.3 125
5.0 150
100
125
tPLH Propagation Delay , Clock to Q or Q
(Figure 1)
3.3 4.0 13.5 3.5 16.0
5.0 2.5 10.0 2.0 10.5
tPHL Propagation Delay , Clock to Q or Q
(Figure 1)
3.3 3.0 14.0 3.0 14.5
5.0 2.0 10.0 1.5 10.5
tPLH Propagation Delay , Set or Reset to Q or Q
(Figure 2)
3.3 3.0 12.0 2.5 13.0
5.0 2.5 9.0 2.0 10.0
tPHL Propagation Delay , Set or Reset to Q or Q
(Figure 2)
3.3 3.0 12.0 3.0 13.5
5.0 2.0 9.5 2.0 10.5
CIN Maximum Input Capacitance
5.0 4.5
4.5
Unit
MHz
ns
ns
ns
ns
pF
CPD Power Dissipation Capacitance
*Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
Typical @25°C,VCC=5.0 V
35
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns)
Symbol
Parameter
VCC*
V
tsu Minimum Setup Time, J or K to Clock (Figure
3)
th Minimum Hold Time, Clock to J or K (Figure
3)
tw Minimum Pulse Width, Set, Reset, Clock
(Figures 1,2)
trec Minimum Recovery Time, Set or Reset to
Clock (Figure 2)
*Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Guaranteed Limits
25 °C
-40°C to
85°C
6.5 7.5
4.5 5.0
00
0.5 0.5
4.0 4.5
3.5 3.5
00
00
Unit
ns
ns
ns
ns
4
4페이지 | |||
구 성 | 총 6 페이지수 | ||
다운로드 | [ KK74AC109.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
KK74AC10 | Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS | KODENSHI KOREA |
KK74AC109 | Dual J-K Flip-Flop | KODENSHI KOREA |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |