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PDF TS87C52X2 Data sheet ( Hoja de datos )
| Número de pieza | TS87C52X2 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
• High-speed Architecture
• 40 MHz at 5V, 30 MHz at 3V
• X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)
• Dual Data Pointer
• On-chip ROM/EPROM (8Kbytes)
• Programmable Clock Out and Up/Down Timer/Counter 2
• Asynchronous Port Reset
• Interrupt Structure with
– 6 Interrupt Sources
– 4 Level Priority Interrupt System
• Full Duplex Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Low EMI (Inhibit ALE)
• Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
• Once Mode (On-chip Emulation)
• Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
• Temperature Ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions
of the 80C51 CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and an X2 speed improve-
ment mechanism.
The fully static design of the TS80C52X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C52X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
www.DataSheet4U.com
8-bit
Microcontroller
8 Kbytes
ROM/OTP,
ROMless
TS80C32X2
TS87C52X2
TS80C52X2
AT80C32X2
AT80C52X2
AT87C52X2
Rev. 4184I–8051–02/08
1 page  
Pin Configuration
P1.0 / T2 1
P1.1 / T2EX 2
P1.2 3
P1.3 4
P1.4 5
P1.5 6
P1.6
P1.7
RST
7
8
9
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
10
11
PDIL/
12 CDIL40
13
P3.4/T0 14
P3.5/T1 15
P3.6/WR 16
P3.7/RD 17
XTAL2 18
XTAL1 19
VSS 20
40 VCC
39 P0.0 / A0
38 P0.1 / A1
37 P0.2 / A2
36 P0.3 / A3
35 P0.4 / A4
34 P0.5 / A5
33 P0.6 / A6
32 P0.7 / A7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 / A15
27 P2.6 / A14
26 P2.5 / A13
25 P2.4 / A12
24 P2.3 / A11
23 P2.2 / A10
22 P2.1 / A9
21 P2.0 / A8
TS8xCx2X2
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P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6 5 4 3 2 1 44 43 42 41 40
7
8
9
10
11
12 PLCC/CQPJ 44
13
39
38
37
36
35
34
33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5
6
7
PQFP44
VQFP44
29
28
27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4184I–8051–02/08
5
5 Page 
Application
TS8xCx2X2
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Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destina-
tion" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,atDPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX atDPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
4184I–8051–02/08
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TS87C52X2.PDF ] | |
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