PDF LC72136N Data sheet ( Hoja de datos )

Número de pieza	LC72136N
Descripción	PLL Frequency Synthesizer for Electronic Tuning
Fabricantes	Sanyo Semicon Device
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No Preview Available ! Ordering number : EN5608 CMOS LSI LC72136N, 72136NM PLL Frequency Synthesizer for Electronic Tuning Overview The LC72136N and LC72136NM are PLL frequency synthesizers for use in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily. Features • High-speed programmable frequency divider — FMIN: 10 to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) — AMIN: 2 to 40 MHz.........Pulse swallower 0.5 to 10 MHz......Direct division • IF counter IFIN: 0.4 to 12 MHz................For use as an AM/FM IF counter • Reference frequency — Selectable from one of eight frequencies (crystal oscillator: 75 kHz) 1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz • Phase comparator — Supports dead zone control — Built-in unlock detection circuit — Built-in deadlock clear circuit • Built-in MOS transistor for forming an active low-pass filter • I/O ports — Dedicated output ports: 6 — I/O ports: 2 — Supports clock time base output • Serial Data I/O — Supports CCB format communication with the system controller. • Operating ranges — Supply voltage: 4.5 to 5.5 V — Operating temperature: –20 to +70°C • Packages —DIP22S/MFP24S Package Dimensions unit: mm 3059-DIP22S [LC72136N] unit: mm 3112-MFP24S [LC72136NM] • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO: DIP22S SANYO: MFP24S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3096HA (OT) No. 5608-1/23 1 page LC72136N, 72136NM Electrical Characteristics at Ta = –20 to +70°C, VSS = 0 V Parameter Internal feedback resistors Internal pull-down resistors Internal output resistor Hysteresis Output high-level voltage Output low-level voltage Input high-level voltage Input low-level current Output off leakage current High-level tree-state off leakage current Low-level tree-state off leakage current Input capacitance Current drain Symbol Rf1 Rf2 Rf3 Rf4 Rpd1 Rpd2 Rd VHIS VOH1 VOL1 VOL2 VOL3 VOL4 VOL5 IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 IIL3 IIL4 IIL5 IIL6 IOFF1 IOFF2 IOFFH Conditions XIN FMIN AMIN IFIN FMIN AMIN XOUT CE, CL, DI, IO1, IO2 PD: IO = –1 mA PD: IO = 1 mA BO1: IO = 0.5 mA BO1: IO = 1 mA DO: IO = 1 mA DO: IO = 5 mA BO2 to BO5, BOF, IO1, IO2: IO = 1 mA BO2 to BO5, BOF, IO1, IO2: IO = 5 mA BO2 to BO5, BOF, IO1, IO2: IO = 8 mA AOUT: IO = 1 mA, AIN = 1.3 V CE, CL, DI: VI = 6.5 V IO1, IO2: VI = 13 V XIN: VI = VDD FMIN, AMIN: VI = VDD IFIN: VI = VDD AIN: VI = 6.5 V CE, CL, DI: VI = 0 V IO1, IO2: VI = 0 V XIN: VI = 0 V FMIN, AMIN: VI = 0 V IFIN: VI = 0 V AIN: VI = 0 V BO1 to BO5, BOF, AOUT, IO1, IO2: VO = 13 V DO: VO = 6.5 V PD: VO = VDD min VDD – 1.0 typ 8.0 500 500 250 200 200 250 0.1 VDD 0.3 0.6 4.0 8.0 0.3 0.6 4.0 8.0 0.01 IOFFL CIN IDD1 IDD2 IDD3 PD: VO = 0 V FMIN VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 40 mVrms VDD: PLL block stopped (PLL inhibit), Xtal oscillator operating (Xtal = 75 kHz) VDD: PLL block stopped, Xtal oscillator stopped 0.01 6 5 0.1 max 1.0 0.5 1.0 0.2 1.0 0.2 1.0 1.6 0.5 5.0 5.0 1.4 22 44 200 5.0 5.0 1.4 22 44 200 5.0 5.0 200 200 10 10 Unit MΩ kΩ kΩ kΩ kΩ kΩ kΩ V V V V V V V V V V V µA µA µA µA µA nA µA µA µA µA µA nA µA µA nA nA pF mA mA µA No. 5608-5/23 5 Page LC72136N, 72136NM Continued from preceding page. No. Control block/data DO pin control data DOC0, DOC1, DOC2 Description • Data that determines DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 DO pin state Open Low when the unlock state is detected end-UC1 Open Open The IO1 pin state2 The IO2 pin state2 Open The open state is selected following a power-on reset. Note: 1. end-UC: IF counter measurement completion check (6) Related data UL0, UL1, CTE, IOC1, IOC2 Unlock detection data UL0, UL1 (7) Phase comparator control data DZ0, DZ1 (8) When end-UC is set and an IF count is started (CTE = 0 → 1), the DO pin automatically goes to the open state. When the IF count measurement completes, the DO pin goes low and the count completion check operation is enabled. The DO pin goes to the open state due to serial data I/O (CE: high). 2. Goes to the open state if the IO pin itself is set to be an output port. Caution: The DO pin always goes to the open state during the data input period (during the period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal DO serial data in synchronization with the CL pin signal during the data output period (during the period when CE is high in the OUT mode) regardless of the values of the DO pin control data (DOC0 to DOC2). • Selects the phase error (øE) detection range for PLL lock discrimination. When a phase error greater than the specified range occurs, the LC72136N determines that the PLL is unlocked. (: Don’t care.) UL1 UL0 øE detection width Detector output 0 0 Stopped Open 0 10 øE is output directly 1 * ±6.67 µs øE is extended by 1 to 2 ms Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0. • Phase comparator dead zone control data DOC0, DOC1, DOC2 DZ1 DZ0 0 0 DZA 0 1 DZB 1 0 DZC 1 1 DZD Dead zone mode Dead zone width: DZA < DZB < DZC < DZD (9) Clock time base TBC • An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1. (The BO1 data will be ignored.) BO1 Charge pump control data • Data that forcibly controls the charge pump output DLC DLC Charge pump output 0 Normal operation 1 Forced low (10) Note: The LC72136N provides a technique for escaping from deadlock by setting Vtune to VCC (deadlock clearing circuit). This is used when the circuit is deadlocked due to the VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V. This function goes to the forced low state (DLC = 1) following a power on reset. The crystal oscillator circuit must be operating normally before this data is changed to return to the normal operating (DLC = 0) state. Continued on next page. No. 5608-11/23 11 Page

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