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AD9269 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9269은 전자 산업 및 응용 분야에서
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부품번호 AD9269 기능
기능 1.8 V Dual Analog-to-Digital Converter
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AD9269 데이터시트, 핀배열, 회로
Data Sheet
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
AD9269
SPI
ADC
PROGRAMMING DATA
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
QUADRATURE
ERROR
CORRECTION
ADC
DIVIDE DUTY CYCLE
1 TO 6 STABILIZER
MODE
CONTROLS
ORA
D15A
D0A
DCOA
DRVDD
ORB
D15B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9269 pdf, 반도체, 판매, 대치품
AD9269
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential
Nonlinearity
(DNL)2
Integral Nonlinearity
(INL)2
MATCHING
CHARACTERISTICS
Offset Error
Gain Error1
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage
(1 V Mode)
Load Regulation
Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
25°C
AD9269-20/AD9269-40
Min Typ
Max
16
Guaranteed
±0.05
±0.40
−2.0
−0.9/+1.2
−0.5/+0.6
±2.0
±5.50
±0.0 ±0.50
±0.2
±2
0.981 0.993
2
1.005
2.8
ANALOG INPUT
Input Span,
VREF = 1.0 V
Full
2
Input Capacitance3 Full
6.5
Input Common-
Mode Voltage
Full
0.9
Input Common-
Mode Range
Full 0.5
1.3
REFERENCE INPUT
RESISTANCE
Full
7.5
POWER SUPPLIES
Supply Voltage
AVDD
Full 1.7 1.8
1.9
DRVDD
Full 1.7
3.6
Supply Current
IAVDD2 Full 50.0/69.3 52.5/72.6
IDRVDD2 (1.8 V) Full
3.9/6.4
IDRVDD2 (3.3 V) Full
7.4/12.4
AD9269-65
Min Typ
Max
16
AD9269-80
Min Typ
Max
16
Unit
Bits
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.4
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.65
% FSR
% FSR
LSB
−0.5/+1.1
±6.50
±2.2
−0.5/+1.1
±6.50
±3.3
LSB
LSB
LSB
±0.0 ±0.55
±0.2
±2
±0.0
±0.65
% FSR
±0.2 % FSR
±2 ppm/°C
0.981 0.993
2
1.005
0.981 0.993
2
1.005
V
mV
2.8
2
6.5
0.9
0.5
7.5
2.8
2
6.5
0.9
1.3 0.5
7.5
1.3
LSB
rms
V p-p
pF
V
V
kΩ
1.7 1.8
1.7
96.6
9.6
18.7
1.9
3.6
101.2
1.7 1.8
1.7
113
11.8
23
1.9
3.6
119
V
V
mA
mA
mA
Rev. A | Page 4 of 40

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AD9269 전자부품, 판매, 대치품
Data Sheet
AD9269
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9269-20/AD9269-40/AD9269-65/AD9269-80
Min Typ
Max
Unit
0.2
GND − 0.3
−10
−10
8
CMOS/LVDS/LVPECL
0.9
10
4
3.6
AVDD + 0.2
+10
+10
12
V
V p-p
V
µA
µA
pF
1.2
0
−50
−10
30
2
DRVDD + 0.3
0.8
−75
+10
V
V
µA
µA
pF
1.2
0
−10
40
26
2
DRVDD + 0.3
0.8
+10
135
V
V
µA
µA
pF
1.2
0
−10
40
26
5
DRVDD + 0.3
0.8
+10
130
V
V
µA
µA
pF
3.29 V
3.25 V
0.2 V
0.05 V
1.79 V
1.75 V
0.2 V
0.05 V
1 Internal 30 kΩ pull-down.
2 Internal 30 kΩ pull-up.
Rev. A | Page 7 of 40

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