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PDF LPC1313 Data sheet ( Hoja de datos )
| Número de pieza | LPC1313 | |
| Descripción | 32-bit ARM Cortex-M3 microcontroller/ up to 32 kB flash and 8 kB SRAM/ USB device | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC1311/13/42/43
www.DataSheet4U.com
32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and
8 kB SRAM; USB device
Rev. 01 — 11 December 2009
Product data sheet
1. General description
The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash
memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus
I2C-bus interface, one UART, four general purpose timers, and up to 42 general purpose
I/O pins.
2. Features
I ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
I ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
I 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
I 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
I Selectable boot-up: UART or USB (USB on LPC134x only).
I Serial interfaces:
N USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
N UART with fractional baud rate generation, modem, internal FIFO, and
RS-485/EIA-485 support.
N SSP controller with FIFO and multi-protocol capabilities.
N I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
I Other peripherals:
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
LPC131w1ww/.D1a3taS/h4eet24U/.c4om3
32-bit ARM Cortex-M3 microcontroller
PIO2_6 1
PIO2_0/DTR 2
RESET/PIO0_0 3
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 4
VSSIO 5
XTALIN 6
XTALOUT 7
VDD(IO) 8
PIO1_8/CT16B1_CAP0 9
PIO0_2/SSEL/CT16B0_CAP0 10
PIO2_7 11
PIO2_8 12
LPC1343FBD48
36 PIO3_0
35 TRST/PIO1_2/AD3/CT32B1_MAT1
34 TDO/PIO1_1/AD2/CT32B1_MAT0
33 TMS/PIO1_0/AD1/CT32B1_CAP0
32 TDI/PIO0_11/AD0/CT32B0_MAT3
31 PIO2_11/SCK
30 PIO1_10/AD6/CT16B1_MAT1
29 SWCLK/PIO0_10/SCK/CT16B0_MAT2
28 PIO0_9/MOSI/CT16B0_MAT1/SWO
27 PIO0_8/MISO/CT16B0_MAT0
26 PIO2_2/DCD
25 PIO2_10
002aae505
Fig 2. LPC1343 LQFP48 package
LPC1311_13_42_43_1
Product data sheet
Rev. 01 — 11 December 2009
© NXP B.V. 2009. All rights reserved.
5 of 53
5 Page 
NXP Semiconductors
LPC131w1ww/.D1a3taS/h4eet24U/.c4om3
32-bit ARM Cortex-M3 microcontroller
Table 3. LPC1313/43 LQFP48 pin description table …continued
Symbol
Pin Type Description
PIO2_4
19[1] I/O
PIO2_4 — General purpose digital input/output pin (LPC1313 only).
PIO2_5
21[1] I/O
PIO2_5 — General purpose digital input/output pin (LPC1343 only).
PIO2_5
20[1] I/O
PIO2_5 — General purpose digital input/output pin (LPC1313 only).
PIO2_6
1[1] I/O
PIO2_6 — General purpose digital input/output pin.
PIO2_7
11[1] I/O
PIO2_7 — General purpose digital input/output pin.
PIO2_8
12[1] I/O
PIO2_8 — General purpose digital input/output pin.
PIO2_9
24[1] I/O
PIO2_9 — General purpose digital input/output pin.
PIO2_10
25[1] I/O
PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK
31[1] I/O
PIO2_11 — General purpose digital input/output pin.
I/O SCK — Serial clock for SSP.
PIO3_0
36[1] I/O
PIO3_0 — General purpose digital input/output pin.
PIO3_1
37[1] I/O
PIO3_1 — General purpose digital input/output pin.
PIO3_2
43[1] I/O
PIO3_2 — General purpose digital input/output pin.
PIO3_3
48[1] I/O
PIO3_3 — General purpose digital input/output pin.
PIO3_4
18[1] I/O
PIO3_4 — General purpose digital input/output pin (LPC1313 only).
PIO3_5
21[1] I/O
PIO3_5 — General purpose digital input/output pin (LPC1313 only).
USB_DM
19[4] I/O
USB_DM — USB bidirectional D− line (LPC1343 only).
USB_DP
20[4] I/O
USB_DP — USB bidirectional D+ line (LPC1343 only).
VDD(IO)
VDD(3V3)
8[5]
44[5]
I
I
3.3 V input/output supply voltage.
3.3 V supply voltage to the internal regulator and the ADC. Also used as the
ADC reference voltage.
VSSIO
XTALIN
5I
6[6] I
Ground.
Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT
7[6] O
Output from the oscillator amplifier.
VSS
41 I
Ground.
[1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[4] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only).
[5] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference
between both supplies is smaller than or equal to 0.5 V.
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
LPC1311_13_42_43_1
Product data sheet
Rev. 01 — 11 December 2009
© NXP B.V. 2009. All rights reserved.
11 of 53
11 Page | ||
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| PDF Descargar | [ Datasheet LPC1313.PDF ] | |
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