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PDF LC72341 Data sheet ( Hoja de datos )
| Número de pieza | LC72341 | |
| Descripción | Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN*5799
Preliminary
CMOS IC
LC72341G/W, LC72342G/W, LC72343G/W
Low-Voltage Single-Chip Microcontrollers with On-
Chip PLL and LCD Driver Circuits
Overview
The LC72341G/W, LC72342G/W, and LC72343G/W are
single-chip microcontrollers with both a 1/4-duty 1/2-bias
LCD driver circuit and a PLL circuit that can operate at up
to 250 MHz integrated on the same chip. These ICs are
ideal for use in portable audio equipment.
Reference frequencies of 1, 3, 5, 6.25, 12.5, and
25 kHz can be provided.
• Input frequency range
— FM band: 10 to 130 MHz
130 to 250 MHz
— AM band: 0.5 to 15 MHz
Functions
• High-speed programmable divider
• Program memory (ROM)
— LC72341G/W: 2048 words × 16 bits (4KB)
— LC72342G/W: 3072 words × 16 bits (6KB)
— LC72343G/W: 4096 words × 16 bits (8KB)
• Data memory (RAM)
— LC72341G/W: 128 words × 4 bits
— LC72342G/W: 192 words × 4 bits
— LC72343G/W: 256 words × 4 bits
• Instruction cycle time
— 40 µs (for all single-word instructions.)
• Stack
— 4 levels (LC72341G/W)
— 8 levels (LC72342G/W, and LC72343G/W)
• LCD driver
— 48 to 80 segments (1/4-duty 1/2-bias drive)
• Timer interrupts
— One timer circuit providing intervals of 1, 5, 10, and
50 ms.
• External interrupts
— One external interrupt (INT)
• A/D converter
— Two channels (5-bit successive approximation)
• Input ports
— 7 (Of which two can be switched to function as A/D
converter inputs)
• Output ports
— 6 (Of which one can be switched to function as the
BEEP tone output. Two ports are open-drain ports.)
• I/O
ports
— 16 (Of which 8 can be selected to function as LCD
ports as mask options.)
• PLL circuit
— Two types of dead band control are supported, and an
unlock detection circuit is included.
Package Dimensions
unit: mm
3159-QFP64G
[LC72341G, 72342G, 72343G]
SANYO: QFP64G
unit: mm
3159-SQFP64
[LC72341W, 72342W, 72343W]
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31398RM (OT) No. 5799-1/12
1 page  
LC72341G/W, 72342G/W, 72343G/W
Note: C1, C2, and C3 must be provided even if no LCD is used.
Electrical Characteristics at Ta = –30 to 70°C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter
Symbol
Conditions
VOH1 PB : IO = –1 mA
VOH2 PC, PD, PG, PH : IO = –1 mA
VOH3 EO : IO = –500 µA
Output high-level voltage
VOH4 XOUT : IO = –200 µA
VOH5 S1 to S20 : IO = –20 µA: *1
COM1, COM2, COM3, COM4:
VOH6 IO = –100 µA : *1
VOL1 PB : IO = –50 µA
VOL2 PC, PD, PE, PG, PH : IO = –1 mA
VOL3 EO : IO = –500 µA
VOL4 XOUT : IO = –200 µA
Output low-level voltage
VOL5 S1 to S20 : IO = –20 µA: *1
VOL6
COM1, COM2, COM3, COM4 :
IO = –100 µA : *1
VOL7 PE : IO = 5 mA
VOL8 AOUT : IO = 1 mA, AIN = 1.3 V, VDD = 3 V
Output off leakage current
IOFF1
IOFF2
Ports PB, PC, PD, PG, PH, and EO
Ports AOUT and PE
A/D conversion error
ADI0, ADI1, VDD = VDD1
Note: 1. Capacitors C1, C2, and C3 must be connected to the DBR pins.
min
VDD – 0.7 VDD
VDD – 0.3 VDD
VDD – 0.3 VDD
VDD – 0.3 VDD
2.0
Ratings
typ
2.0
–3
–100
–1/2
max
0.7 VDD
0.3 VDD
0.3 VDD
0.3 VDD
1.0
1.0
1.0
0.5
+3
+100
+1/2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
nA
LSB
Electrical Characteristics at Ta = –20 to 70°C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter
Symbol
Conditions
Falling supply voltage detection voltage
Rising supply voltage detection voltage
Pull-down resistance
Supply current
VSENSE1
VSENSE2
RPD2
IDD1
IDD2
IDD3
Ta = 25°C *2
Ta = 25°C *2
TEST1, TEST2
VDD1 : FIN2 130 MHz, Ta = 25°C
VDD2: In halt mode at Ta = 25°C, *3
VDD = 3.6 V, with the oscillator stopped,
at Ta = 25°C, *4
IDD4
VDD = 1.8 V, with the oscillator stopped,
at Ta = 25°C, *4
Note: The halt mode current is measured with the CPU executing 20 instructions every 125 ms.
min
1.6
VSENSE1 +0.1
Ratings
typ
1.75
10
10
0.1
max
1.9
VSENSE1 +0.2
Unit
V
V
kΩ
mA
mA
1 µA
0.5 µA
No. 5799-5/12
5 Page 
LC72341G/W, 72342G/W, 72343G/W
Instruction Set
Instruction
Mnemonic
group
AD
ADS
AC
ACS
AI
AIS
AIC
AICS
SU
SUS
SB
SBS
SI
SIS
SIB
SIBS
SEQ
SEQI
SNEI
SGE
SGEI
SLEI
ANDI
ORI
EXLI
AND
OR
EXL
SHR
LD
ST
MVRD
MVRS
MVSR
Memory
test
instructions
MVI
TMT
TMF
JMP
CAL
RT
RTI
SS
RS
TST
TSF
TUL
Opcode
1st 2nd
rM
rM
rM
rM
MI
MI
MI
MI
rM
rM
rM
rM
MI
MI
MI
MI
rM
MI
MI
rM
MI
MI
MI
MI
MI
rM
rM
rM
r
rM
Mr
rM
Mr
M1 M2
MI
MN
MN
ADDR
ADDR
IN
IN
IN
IN
N
Machine code
15 12 11 8 7
43
0
Operation
0100 00 DH DL
r r ← (r) + (M)
0100 01 DH DL
r r ← (r) + (M), skip if carry
0100 10 DH DL
r r ← (r) + (M) + C
0100 11 DH DL
r r ← (r) + (M) + C, skip if carry
0101 00 DH DL
I M ← (M) + I
0101 01 DH DL
I M ← (M) + I, skip if carry
0101 10 DH DL
I M ← (M) + I + C
0101 11 DH DL
I M ← (M) + I + C, skip if carry
0110 00 DH DL
r r ← (r) – (M)
0110 01 DH DL
r r ← (r) – (M), skip if borrow
0110 10 DH DL
r r ← (r) – (M) – b
0110 11 DH DL
r r ← (r) – (M) – b, skip if borrow
0111 00 DH DL
I M ← (M) – I
0111 01 DH DL
I M ← (M) – I, skip if borrow
0111 10 DH DL
I M ← (M) – I – b
0111 11 DH DL
I M ← (M) – I – b, skip if borrow
0001 00 DH DL
r (r) ← (M), skip if zero
0001 10 DH DL
I (M) — I, skip if zero
0000 01 DH DL
I (M) — I, skip if not zero
0001 10 DH DL
r (r) — (M), skip if not borrow
0001 11 DH DL
I (M) — I, skip if not borrow
0000 11 DH DL
I (M) — I, skip if borrow
0010 01 DH DL
I M ← (M) AND I
0010 11 DH DL
I M ← (M) OR I
0011 10 DH DL
I M ← (M) XOR I
0010 00 DH DL
r r ← (r) AND M
0010 10 DH DL
r r ← (r) OR M
0011 00 DH DL
r r ← (r) XOR M
0000 00 00 1110
r Shift r right with carry
1101 00 DH DL
r r ← (M)
1101 01 DH DL
r M ← (r)
1101 10 DH DL
r [DH, rn] ← (M)
1101 11 DH DL
r M ← [DH, rn]
1110 00 DH DL1
DL2 [DH, DL1] ← [DH, DL2]
1110 01 DH DL
I M←I
1111 00 DH DL
N if M (N) = all 1, then skip
1111 01 DH DL
N if M (N) = all 0, then skip
100 ADDR (13 bits) PC ← ADDR
101 ADDR (13 bits) PC ← ADDR, Stack ← (PC) + 1
0000
0000
1000
PC ← Stack
0000
0000
1001
PC ← Stack, BANK ← Stak, carry ← stack
1111
1111
000 I
N (Status reg. I)N ← 1
1111
1111
001 I
N (Status reg. I)N ← 0
1111
1111
01 I
N if (Status reg. I)N = all 1, then skip
1111
1111
10 I
N if (Status reg. I)N = all 0, then skip
0000
0000
1101
N if Unlock F/F (N) = all 0, then skip
Continued on next page.
No. 5799-11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LC72341.PDF ] | |
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