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PDF AS1525 Data sheet ( Hoja de datos )
| Número de pieza | AS1525 | |
| Descripción | 1-Channel Pseudo/True-Differential and 2-Channel Single-Ended ADCs | |
| Fabricantes | austriamicrosystems AG | |
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Datasheet
www.DataSheet4U.com
AS1524/AS1525
150ksps, 12-Bit, 1-Channel Pseudo/True-Differential
and 2-Channel Single-Ended ADCs
1 General Description
2 Key Features
The AS1524/AS1525 are low-power, 12-bit analog-to-
digital converters (ADCs) designed to operate with a sin-
gle +2.7V to +5.25V supply. Excellent dynamic perfor-
mance, low power consumption, and simplicity make
these devices perfect for portable battery-powered data-
acquisition applications.
The devices are available as the standard products
listed in Table 1.
Table 1. Standard Products
Model
Input Type
Input Voltage
AS1524
1-Channel, Pseudo /
True-Differential
0 to VREF /
-VREF/2 to VREF/2
AS1525
2-Channel, Single-
Ended
0 to VREF
! Single-Supply Operation: +2.7V to +5.25V
! Automatic Shutdown Between Conversions
! Low Power Consumption
- 350µA @ 150ksps
- 245µA @ 100ksps
- 24µA @ 10ksps
- 2.5µA @ 1ksps
- 200nA in Automatic Shutdown Mode
! True-Differential Track/Hold, 150kHz Sampling Rate
Software-Configurable Unipolar/Bipolar Conversion
(AS1524)
The devices feature a successive-approximation regis-
ter (SAR), automatic shutdown, fast wakeup (1.4µs),
and low-power consumption at the maximum sampling
rate of 150ksps.
Automatic shutdown (0.2µA) between conversions
results in reduced power consumption (at slower
throughput rates).
Data access are made via an external clock through the
SPI-/QSPI-/MICROWIRE-compatible 3-wire high-speed
serial interface.
The AS1525/AS1524 are available in a 8-pin TDFN
(3x3mm) package.
Figure 1. AS1524/AS1525 - Block Diagram
! Input Common Mode Range from GND to VDD
! 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
! Internal Conversion Clock
! 8-pin TDFN (3x3mm) Package
3 Applications
The devices are ideal for remote sensors, data-acquisi-
tion, data logging devices, lab instruments, or for any
other space-limited A/D devices with low power con-
sumption and single-supply requirements.
1
VDD
7
CNVST
8
SCLK
2
AIN1/AIN+
2
AIN2/AIN-
4
REF
AS1524/AS1525
Input
Shift
Register
Osc
Control
Logic
Track/
Hold
12-Bit
SAR
6
DOUT
5
GND
www.austriamicrosystems.com
Revision 1.02
1 - 22
1 page  
AS1524/AS1525
Datasheet - Electrical Characteristics
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6 Electrical Characteristics
VDD = +2.7 to +5.25V, VREF = +2.5V, 4.7µF Capacitor at REF; fSCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1524)
TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25ºC. Unipolar Mode (AS1524).
Table 4. Electrical Characteristics
Symbol
Parameter
Condition
Min Typ Max Unit
DC Accuracy
Resolution
12 Bits
INL Relative Accuracy
±1.0 LSB
DNL
Differential Non-Lineraity No Missing Codes Over Temperature -0.99
+1.0 LSB
Offset Error
±1 ±4 LSB
Gain Error 1
±1 ±4 LSB
Gain Temp Coefficient
±0.3 ppm/ºC
Offset Temp Coefficient
±0.3 ppm/ºC
Channel-to-Channel Offset
Match
±0.1 LSB
Channel-to-Channel Gain
Match
±0.1 LSB
Dynamic Specifications – (fIN (sinewave) = 10kHz, VIN = 2.5VP-P, 150ksps, fSCLK = 8MHz (50% duty cycle), AIN- =
GND (AS1524)
SINAD Signal-to-Noise Plus Distortion
72.5 dB
THD
Total Harmonic Distortion (to
the 5th Harmonic)
-79.5
dB
SFDR Spurious-Free Dynamic Range
84 dB
Full Power Bandwidth
-3dB Point
20 MHz
Full Linear Bandwidth
-0.1dB Point
400 kHz
Conversion Rate
tCONV
Conversion Time
Exclusive of tACQ
3.3 3.7
µs
tACQ Track/Hold Acquisition Time
1.4 µs
Aperture Delay
30 ns
fSCLK Max Serial Clock Frequency
8 MHz
Serial Clock Duty Cycle
30 70 %
Analog Input
VIN Range 2
Unipolar
Bipolar
0
-VREF/2
VREF
VREF/2
V
Input Leakage Current
No Channel Selected or Conversion
Halted
±0.01 ±1
µA
Input Capacitance
Track Mode
Hold Mode
20 pF
5 pF
External Reference Input
VREF
VIN Range
1.0
VDD +
50mV
V
VREF = +2.5V @ 150ksps
11 25
IREF Input Current
VREF = +4.096V @ 150ksps
19 µA
Acquisition Between Conversions
0 +2 +5
www.austriamicrosystems.com
Revision 1.02
5 - 22
5 Page 
AS1524/AS1525
Datasheet - Detailed Description
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8 Detailed Description
The AS1524/AS1525 employ a successive approximation conversion (SAR) technique and integrated track/hold cir-
cuitry to convert analog signals into 12-bit digital output. The serial interface provides easy interfacing to microproces-
sors. Figure 18 shows the simplified internal structure for the AS1525 (2-channels, single ended) and the AS1524
(1-channel, true differential).
True Differential Analog Input Track/Hold
The equivalent circuit of Figure 18 shows the device input architecture which is composed of track/hold circuitry, input
multiplexer, comparator, and switched-capacitor DAC. The track/hold circuitry enters its tracking mode on the rising
edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (AS1525) or AIN+ (AS1524). The negative
input capacitor is connected to GND (AS1525) or AIN- (AS1524).
Figure 18. Equivalent Input Circuit
AIN2
AIN1/AIN+
GND/AIN-
Hold
REF
GND
12-Bit Capacitive DAC
CIN+
CIN-
RIN-
RIN+
+
–
Comparator
Hold
VDD/2
Track
Hold
The track/hold circuitry enters its hold mode on the falling edge of CNVST and the difference between the sampled
positive and negative input voltages is converted. The time required for the track/hold to acquire an input signal is
determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisi-
tion time lengthens, and CNVST must be held high for a longer period of time. The acquisition time (tACQ) is the maxi-
mum time needed for the signal to be acquired, plus the power-up time. tACQ is calculated by:
tACQ = 9 x (RS + RIN) x 20pF + tPWR
(EQ 1)
Where:
RS is the source impedance of the input signal;
RIN = 1.5kΩ;
tPWR of 1µs is the power-up time of the device.
Note: tACQ is never less than 1.4µs and any source impedance below 300. does not significantly affect the AS1524/
AS1525 AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by
placing a 1µF capacitor between the positive and negative analog inputs.
Selecting AIN1 or AIN2 (AS1525)
Select one of the AS1525 two positive input channels using the CNVST pin (see page 3). If AIN1 is selected (see Fig-
ure 19), drive CNVST high to power up the AS1525 and place the track/hold circuitry in track mode with AIN1 con-
nected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place
the track/hold circuitry in hold mode. The AS1525 then performs a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving
CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is
selected for the next conversion.
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Revision 1.02
11 - 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AS1525.PDF ] | |
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