Datasheet.kr   

LC72342W 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC72342W은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 LC72342W 자료 제공

부품번호 LC72342W 기능
기능 Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits
제조업체 Sanyo Semicon Device
로고 Sanyo Semicon Device 로고


LC72342W 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 12 페이지수

미리보기를 사용할 수 없습니다

LC72342W 데이터시트, 핀배열, 회로
Ordering number : EN*5799
Preliminary
CMOS IC
LC72341G/W, LC72342G/W, LC72343G/W
Low-Voltage Single-Chip Microcontrollers with On-
Chip PLL and LCD Driver Circuits
Overview
The LC72341G/W, LC72342G/W, and LC72343G/W are
single-chip microcontrollers with both a 1/4-duty 1/2-bias
LCD driver circuit and a PLL circuit that can operate at up
to 250 MHz integrated on the same chip. These ICs are
ideal for use in portable audio equipment.
Reference frequencies of 1, 3, 5, 6.25, 12.5, and
25 kHz can be provided.
• Input frequency range
— FM band: 10 to 130 MHz
130 to 250 MHz
— AM band: 0.5 to 15 MHz
Functions
• High-speed programmable divider
• Program memory (ROM)
— LC72341G/W: 2048 words × 16 bits (4KB)
— LC72342G/W: 3072 words × 16 bits (6KB)
— LC72343G/W: 4096 words × 16 bits (8KB)
• Data memory (RAM)
— LC72341G/W: 128 words × 4 bits
— LC72342G/W: 192 words × 4 bits
— LC72343G/W: 256 words × 4 bits
• Instruction cycle time
— 40 µs (for all single-word instructions.)
• Stack
— 4 levels (LC72341G/W)
— 8 levels (LC72342G/W, and LC72343G/W)
• LCD driver
— 48 to 80 segments (1/4-duty 1/2-bias drive)
• Timer interrupts
— One timer circuit providing intervals of 1, 5, 10, and
50 ms.
• External interrupts
— One external interrupt (INT)
• A/D converter
— Two channels (5-bit successive approximation)
• Input ports
— 7 (Of which two can be switched to function as A/D
converter inputs)
• Output ports
— 6 (Of which one can be switched to function as the
BEEP tone output. Two ports are open-drain ports.)
• I/O
ports
— 16 (Of which 8 can be selected to function as LCD
ports as mask options.)
• PLL circuit
— Two types of dead band control are supported, and an
unlock detection circuit is included.
Package Dimensions
unit: mm
3159-QFP64G
[LC72341G, 72342G, 72343G]
SANYO: QFP64G
unit: mm
3159-SQFP64
[LC72341W, 72342W, 72343W]
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31398RM (OT) No. 5799-1/12




LC72342W pdf, 반도체, 판매, 대치품
LC72341G/W, 72342G/W, 72343G/W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN
VOUT1
VOUT2
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
Pd max
Topr
Tstg
Conditions
All input pins
AOUT, PE
All output pins except VOUT1
PC, PD, PG, PH, EO
PB
AOUT, PE
S1 to S20
COM1 to COM4
Ta = –20 to +70°C
Allowable Operating Ranges at Ta = –20 to 70°C, VDD = 1.8 to 3.6 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Input amplitude
Input voltage range
Input frequency
Symbol
Conditions
VDD1
VDD2
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VIN1
VIN2
VIN3
VIN4
VIN5
FIN1
FIN2
FIN3
FIN4
FIN5
FIN6
CPU and PLL operating voltage
Memory retention voltage
VIH2, VIH3, AMIN, FMIN,
Input ports except HCTR and XIN.
RES
Port PF
VIL2, VIL3, AMIN, FMIN,
Input ports except HCTR and XIN.
RES
Port PF
XIN
FMIN, AMIN
FMIN
HCTR
ADI0, ADI1
XIN : CI 35 k
FMIN : VIN2, VDD1
FMIN : VIN3, VDD1
AMIN (H) : VIN2, VDD1
AMIN (L) : VIN2, VDD1
HCTR : VIN4, VDD1
Ratings
–0.3 to +4.0
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD to + 0.3
0 to 3
0 to 1
0 to 2
300
3
300
–20 to +70
–45 to +125
Unit
V
V
V
V
mA
mA
mA
µA
mA
mW
°C
°C
min
1.8
1.0
0.7 VDD
0.8 VDD
0.6 VDD
0
0
0
0.5
0.035
0.05
0.035
0
70
10
130
2
0.5
0.4
Ratings
typ
3.0
75
max
3.6
VDD
VDD
VDD
0.3 VDD
0.2 VDD
0.2 VDD
0.6
0.35
0.35
0.35
VDD
80
130
250
40
10
12
Unit
V
V
V
V
V
V
V
V
Vrms
Vrms
Vrms
Vrms
V
kHz
MHz
MHz
MHz
MHz
MHz
Electrical Characteristics at Ta = –20 to 70°C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter
Input high-level current
Input low-level current
Input floating voltage
Pull-down resistance
Hysteresis
Voltage doubler reference voltage
Voltage doubler step-up voltage
Symbol
Conditions
IIH1 XIN : VI = VDD = 3.0 V
IIH2 FMIN, AMIN, HCTR : VI = VDD = 3.0 V
Ports PA/PF (with no pull-down resistor), PC,
IIH3 PD, PG, and PH. RES: VI = VDD = 3.0 V
IIL1 XIN : VI = VDD = VSS
IIL2 FMIN, AMIN, HCTR : VI = VDD = VSS
Ports PA/PF (with no pull-down resistor), PC,
IIL3 PD, PG, and PH. RES: VI = VDD = VSS
VIF PA/PF with pull-down resistors used
RPD1 PA/PF with pull-down resistors used, VDD = 3 V
VH RES
DBR4 Ta = 25°C, referenced to VDD, C3 = 0.47 µF
DBR1, 2, 3 Ta = 25°C, C1 = 0.45 µF, C2 = 0.47 µF, no load
min
3
–3
75
0.1 VDD
1.3
2.7
Ratings
typ
8
max
3
20
3
–3
–8 –20
–3
100
0.2 VDD
1.5
3.0
0.05 VDD
200
1.7
3.3
Unit
µA
µA
µA
µA
µA
µA
V
k
V
V
V
No. 5799-4/12

4페이지










LC72342W 전자부품, 판매, 대치품
Pin Functions
Pin No.
Pin
64 XIN
1 XOUT
63 TEST1
2 TEST2
6 PA0
5 PA1
4 PA2
3 PA3
LC72341G/W, 72342G/W, 72343G/W
I/O Function
I
Connections for a 75-kHz crystal oscillator element
O
I/O circuit
I
IC test pins. These pins must be tied to ground.
I
Input with built-in pull-
down resistor
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
I presses can be detected. The four pull-down resistors are selected together in a single
operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually.
Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
Unbalanced CMOS
Special-purpose key source signal output ports. Since unbalanced CMOS output push-pull circuit
10 PB3
transistor circuits are used, diodes to prevent short-circuits when multiple keys are
9
PB2
pressed are not required. These ports go to the output high-impedance state in backup
O mode. These ports go to the output high-impedance state after a reset and remain in that
8 PB1
state until an output instruction (OUT, SPB, or RPB) is executed.
7 PB0
Care is required in designing the output loads if these pins are used for functions other
than key source outputs.
14 PC0
13 PC1
CMOS push-pull circuit
12 PC2
General-purpose I/O ports*. PD0 can be used as an external interrupt port. Input or
11 PC3
output mode can be set in a bit unit using the IOS instruction (Pwn = 4, 5). A value of 0
I/O specifies input, and 1 specifies output. These ports go to the input disabled high-
18 INT/PD0
impedance state in backup mode. They are set to function as general-purpose input ports
17 PD1
after a reset.
16 PD2
15 PD3
20 BEEP/PE0
19 PE1
General-purpose output ports with shared beep tone output function (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port.
The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone
frequencies supported.
When PE0 is set up as the beep tone output, executing an output instruction to PN0 only
changes the state of the internal output latch, it does not affect the beep tone output in
any way. Only the PE0 pin can be switched between the general-purpose output
function and the beep tone output function; the PE1 pin only functions as a general-
purpose output. These pins go to the high-impedance state in backup mode and remain
in that state until an output instruction or a BEEP instruction is executed. Since these
ports are open-drain ports, resistors must be inserted between these pins and VDD.
These ports are set to their general-purpose output port function after a reset.
N-channel open drain
General-purpose input and A/D converter input shared function ports (PF2 is a general-
purpose input only port). The IOS instruction (Pwn = FH) is used to switch between the
general-purpose input and A/D converter port functions. The general-purpose input and
CMOS input/analog
input
A/D converter port functions can be switched in a bit unit, with 0 specifying general-
purpose input, and 1 specifying the A/D converter input function. To select the A/D
23 PF0/ADI0
converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1.
The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is
22 PF1/ADI1 I set when the conversion completes. The INR instruction is used to read in the data.
21 PF2
If an input instruction is executed for one of these pins which is set up for analog input,
the read in data will be at the low level since CMOS input is disabled. In backup mode
these pins go to the input disabled high-impedance state. These ports are set to their
general-purpose input port function after a reset. The A/D converter is a 5-bit successive
approximation type converter, and features a conversion time of 1.28 ms. Note that the
full-scale A/D converter voltage (1FH) is (63 · 96)VDD.
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS
instruction when using the I/O switchable ports as output pins.
Continued on next page.
No. 5799-7/12

7페이지


구       성 총 12 페이지수
다운로드[ LC72342W.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
LC72342G

Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits

Sanyo Semicon Device
Sanyo Semicon Device
LC72342W

Low-Voltage Single-Chip Microcontrollers with On- Chip PLL and LCD Driver Circuits

Sanyo Semicon Device
Sanyo Semicon Device

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵