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LC72347 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC72347은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 LC72347 기능
기능 Ultralow-Voltage ETR Controller with On-Chip LCD Driver
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LC72347 데이터시트, 핀배열, 회로
Ordering number : ENN*6651
Preliminary
CMOS IC
LC72346W, 72347W
Ultralow-Voltage ETR Controller
with On-Chip LCD Driver
Overview
The LC72346W and LC72347W are ultralow-voltage
electronic tuning microcontrollers that include a PLL that
operates up to 250 MHz and a 1/4 duty 1/2 bias LCD
driver on chip. This IC includes an on-chip DC-DC
converter that can easily create the power supply voltages
needed for electronic tuning and contribute to reducing
end product costs. This IC is optimal for portable audio
equipment that must operate from a single battery.
Function
• Program memory (ROM):
— 4096 × 16 bits (8K bytes) : LC72346
— 6144 × 16 bits (12K bytes): LC72347
• Data memory (RAM):
— 256 × 4 bits: LC72346
— 512 × 4 bits: LC72347
• Cycle time:
40 µs (all 1-word instructions) at 75kHz crystal oscillation
• Stack: 8 levels
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: Two external interrupts
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter:
Four input channels (6-bit successive approximation
conversion)
• Input ports: 7 ports (of which three can be switched for
use as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are open-drain ports)
• I/O ports: 20 ports (of which 8 can be switched for use
as LCD ports and as mask options, of which 3 can be
switched for use as serial I/O ports)
• Serial I/O: One system (LC72347)
• PLL: Reference frequencies:
1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz
• Input frequencies: FM band: 10 to 250 MHz
AM band (high): 2 to 20 MHz
AM band (low): 0.5 to 10 MHz
• Input sensitivity:
FM band: 35 mVrms (50 mVrms at 130 MHz or higher
frequency)
AM band (high, low): 35 mVrms
• External reset input: During CPU and PLL operations,
instruction execution is started from location 0.
• Built-in power-on reset circuit:
The CPU starts execution from location 0 when power is
first applied.
• Halt mode: The controller-operating clock is stopped.
Continued on next page.
Package Dimensions
unit: mm
3190-SQFP64
[LC72346W, 72347W]
12.0
10.0
1.25 0.5 0.18
48
49
1.25
33
0.15
32
64
1
17
16
0.5 0.5
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1501TN (OT) No. 6651-1/12




LC72347 pdf, 반도체, 판매, 대치품
LC72346W, 72347W
Electrical Characteristics under allowable operating conditions
Parameter
Symbol
Conditions
min
Input high-level current
Input low-level current
Input floating voltage
Pull-down resistor values
Hysteresis
Output high-level voltage
Output low-level voltage
Output off leakage current
A/D converter error
Current drain
IIH1
IIH2
IIH3
IIH4
IIL1
IIL2
IIL3
IIL4
VIF
RPD1
RPD2
VH
VOH1
VOH2
VOH3
VOH4
VOH5
VOH6
VOH7
VOL1
VOL2
VOL3
VOL4
VOL5
VOL6
VOL7
IOFF1
IOFF2
IDD1
IDD2
IDD3
IDD4
XIN: VDD1 = 1.3 V
FMIN, AMIN: VDD1 = 1.3 V
Port PF: VDD1 = 1.3 V
PA (without pull-down resistors), the PC,
PD, PG, and PH ports, and BRES,
PK: VDD1 = 1.3 V
XIN: VDD1 = VSS
FMIN, AMIN: VDD1 = VSS
Port PF: VDD1 = VSS
PA (without pull-down resistors), the PC,
PD, PG, and PH ports, and BRES,
PK: VDD1 = VSS
PA (with pull-down resistors)
3
–3
PA/PF (with pull-down resistors), VDD1 = 1.3 V
TEST1, TEST2 (with pull-down resistors),
VDD1 = 1.3 V
BRES
PB: IO = 1 mA
PC, PD, PG, PH and PK: IO = 1 mA
EO: IO = 500 µA
XOUT: IO = 1 µA
S1 to S20: IO = 20 µA
COM1, COM2, COM3, COM4:
IO = 100 µA
VDC1: IO = 1 mA
PB: IO = –50 µA
PC, PD, PG, PH and PK: IO = –1 mA
EO: IO = –500 µA
XOUT: IO = –1 µA
S1 to S20: IO = –20 µA
COM1, COM2, COM3, COM4:
IO = –100 µA
PE: IO = 2 mA
Ports PB, PC, PD, PG, PK, and EO
75
0.1 VDD1
VDD1 –
0.3 VDD
VDD1 –
0.3 VDD1
VDD4 –
0.3 VDD4
VDD1 –
0.3 VDD1
VDD4 –1
VDD4 –1
VDD4 –1
–3
Port PE
–100
ADI0, ADI1, ADI3 VDD1
VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25°C
VDD1 = 1.3 V: In PLL stop mode, Ta = 25°C
VDD1 = 1.3 V: In HALT mode, Ta = 25°C *1
VDD1 = 1.8 V, with the oscillator stopped,
Ta = 25°C *2
–1/2
Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms.
Ratings
typ
8
–8
100
10
0.2 VDD1
10
0.15
0.1
1
max
3
20
4
3
–3
–20
–4
–3
0.05 VDD1
200
0.3 VDD1
0.3 VDD1
0.3 VDD4
0.3 VDD1
VDD4 –2
VDD4 –2
0.6 VDD1
+3
+100
+1/2
30
Unit
µA
µA
µA
µA
µA
µA
µA
µA
V
k
k
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
nA
LSB
mA
mA
mA
µA
No. 6651-4/12

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LC72347 전자부품, 판매, 대치품
Pin Functions
Pin No.
Pin
I/O
LC72346W, 72347W
Function
64 XIN
I
75 kHz oscillator connections
1 XOUT O
I/O circuit
63 TEST1
2 TEST2
6 PA0
5 PA1
4 PA2
3 PA3
I IC testing.
I These pins must be connected to ground.
Special-purpose ports for key return signal input designed with a low threshold
voltage. When a key matrix is formed in combination with port PB, simultaneous
I
multiple key presses with up to 3 keys can be detected. The pull-down resistors are
set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This
setting cannot be specified for individual pins. In backup mode, these pins go to the
input disabled state, and the pull-down resistors are disabled after a reset.
Input with built-in
pull-down resistor
Unbalanced CMOS push-pull
10 PB0
Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction.
Since these outputs are unbalanced, no diodes are required to prevent short circuits
9 PB1
due to simultaneous multiple key presses. These outputs go to the high-impedance
8 PB2 O output state in backup mode. After a reset, they go to the high-impedance output
7 PB3
state and remain in that state until an output instruction (OUT, SPB, or RPB) is
executed.
14 PC0
13 PC1
12 PC2
General-purpose I/O ports.
11 PC3
PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5)
I/O is used for switching the general-purpose I/O port function, and these ports can be set
18 INT1/PD0
to input or output in 1-bit units. (0: input, 1: output)
17 INT0/PD1
In backup mode they go to the input disabled high-impedance state.
16 PD2
After a reset, they switch to the general-purpose input port function.
15 PD3
*2
CMOS push-pull
20 BEEP/PE0
19 PE1
General-purpose output and beep tone output shared function ports (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output
port. The b0 and b1 bits are used to select the beep tone frequency. There are two
beep tone frequencies supported.
O *: When PE0 is set up as the beep tone output, executing an output instruction to PE0
only changes the state of the internal output latch, it does not affect the beep tone
output in any way. Only the PE0 pin can be switched between the general-purpose
output function and the beep tone output function; the PE1 pin only functions as a
general-purpose output. These pins go to the high-impedance state in backup
mode and remain in that state until an output instruction or a BEEP instruction is
executed. Since these ports are open-drain ports, resistors must be inserted
between these pins and VDD. These ports are set to general-purpose output port
function after a reset.
N-channel open-drain
Shared function pins used as either general-purpose I/O ports or a serial I/O port.
27 PK0
When used as general-purpose I/O ports, the I/O direction can be switched in single
26
SCK1/PK1
pin units with the IOS instruction (with Pwn = C). The IOS instruction (with Pwn = 1,
I/O b2) is used to switch the function between the general-purpose I/O port and the serial
25 SO1/PK2
I/O port function. (0: general-purpose I/O port, 1: serial I/O)
24 SI1/PK3
In backup mode (low power mode) these pins go to the input disabled high-
impedance state. After a reset, the general-purpose input port function is selected.
CMOS push-pull
Continued on next page.
No. 6651-7/12

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