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LC72348W 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC72348W은 전자 산업 및 응용 분야에서
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부품번호 LC72348W 기능
기능 Low-Voltage ETR Controller with On-Chip LCD Driver
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LC72348W 데이터시트, 핀배열, 회로
Ordering number : ENN6472
CMOS IC
LC72348G/W, 72349G/W
Low-Voltage ETR Controller
with On-Chip LCD Driver
Overview
The LC72348G/W and LC72349G/W are low-voltage
electronic tuning microcontrollers that include a PLL that
operates up to 230 MHz and a 1/4 duty 1/2 bias LCD
driver on chip. These ICs can contribute to further end
product cost reduction than the LC72341 series while
providing improved standby current characteristics. Also
these ICs can use the application program for the
LC72341 series except the IF counter function.
These ICs are optimal for use in low-voltage portable
audio equipment that includes a radio receiver.
Package Dimensions
unit: mm
3231-QIP64G
[LC72348G, 72349G]
1.0
48
17.2
14.0
0.8 0.35
1.6
1.0
33
32
49
0.15
Function
• Program memory (ROM):
— 3072 × 16 bits (6K bytes)
— 4096 × 16 bits (8K bytes)
LC72348G/W
LC72349 G/W
• Data memory (RAM):
— 192 × 4 bits LC72348 G/W
— 256 × 4 bits LC72349 G/W
• Cycle time: 40 µs (all 1-word instructions) at 75kHz
crystal oscillation
• Stack: 8 levels
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: One external interrupt
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter: Three input channels
(5-bit successive approximation
conversion)
• Input ports: 7 ports (of which three can be switched for
use as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are open-
drain ports)
• I/O ports: 16 ports (of which 8 can be switched for use
as LCD ports and as mask options)
Continued on next page.
64
1
17
16
0.1
2.15
unit: mm
3190-SQFP64
15.6
0.8
SANYO: QFP64G
[LC72348W, 72349W]
12.0
10.0
1.25
0.5 0.18
1.25
48
49
33
32
0.15
64
1
17
16
0.5 0.5 SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32700RM (OT) No. 6472-1/14




LC72348W pdf, 반도체, 판매, 대치품
LC72348G/W, 72349G/W
Continued from preceding page.
Parameter
Output low-level voltage
Output off leakage current
A/D converter error
Supply voltage drop detection voltage
Supply voltage rise detection voltage
Current drain
Symbol
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
VOL(8)
IOFF(1)
IOFF(2)
VSENSE(1)
VSENSE(2)
IDD(1)
IDD(2)
IDD(3)
IDD(4)
Conditions
PB: IO = –50 µA
PC, PD, PE, PG, PH: IO = –1 mA
EO: IO = –500 µA
XOUT: IO = –1 µA
S1 to S20: IO = –20 µA *1
COM1, COM2, COM3, COM4:
IO = –100 µA *1
PE: IO = 2 mA
AOUT(AIN = 1.3 V), TU: IO = 1 mA, VDD = 3 V
Ports PB, PC, PD, PG, PH, and EO
AOUT and port PE
ADI0, ADI1, ADI3 VDD(4)
Ta = 25°C *2
Ta = 25°C *2
VDD(1): FIN(2) 130 MHz, Ta = 25°C
VDD(2): In HALT mode, Ta = 25°C *3
VDD = 3.6 V, with the oscillator stopped,
Ta = 25°C *4
VDD = 1.8 V, with the oscillator stopped,
Ta = 25°C *4
min
0.3 VDD
–3
–100
–1/2
1.6
(1)min
+0.1
Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.
Pin Assignment
Ratings
typ
1.75
5
0.1
1
max
0.7 VDD
0.3 VDD
0.3 VDD
0.3 VDD
1.0
1.0
1.0
0.5
+3
+100
+1/2
1.9
(1)max
+0.2
15
0.5
Unit
V
V
V
V
V
V
V
V
µA
nA
LSB
V
V
mA
mA
µA
µA
XOUT
TEST2
PA3
PA2
PA1
PA0
PB3
PB2
PB1
PB0
PC3
PC2
PC1
PC0
PD3
PD2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7
LC72348G, 72348W
42
8
LC72349G, 72349W
41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM1
COM2
COM3
COM4
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
No. 6472-4/14

4페이지










LC72348W 전자부품, 판매, 대치품
Pin Functions
Pin No.
Pin
I/O
LC72348G/W, 72349G/W
Function
64 XIN
I
75 kHz oscillator connections
1 XOUT O
I/O circuit
63 TEST1
2 TEST2
6 PA0
5 PA1
4 PA2
3 PA3
I
IC testing. These pins must be connected to ground during normal operation.
I
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
I
presses can be detected. The four pull-down resistors are selected together in a
single operation using the IOS instruction (PWn = 2, b1); they cannot be specified
individually. Input is disabled in backup mode, and the pull-down resistors are
disabled after a reset.
Input with built-in
pull-down resistor
General-purpose CMOS and n-channel open-drain output shared-function ports.
The IOS instruction (Pwn = 2) is used for function switching.
Unbalanced CMOS push-
pull/n-channel open-drain
10 PB0
(b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel open-
drain)
9 PB1
Special-purpose key source signal output ports. Since unbalanced CMOS output
8 PB2 O transistor circuits are used, diodes to prevent short-circuits when multiple keys are
pressed are not required. These ports go to the output high-impedance state in
7 PB3
backup mode. These ports go to the output high-impedance state after a reset and
remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
*: Verify the output impedance conditions carefully if these pins are used for functions
other than key source outputs.
14 PC0
13 PC1
12 PC2
General-purpose I/O ports.
11 PC3
PD0 can be used as an external interrupt port. Input or output mode can be set
I/O individually using the IOS instruction by the bit (Pwn = 4, 5). A value of 0 specifies
18 INT/PD0
input, and 1 specifies output. These ports go to the input disabled high-impedance
17 PD1
16 PD2
state in backup mode. They are set to function as general-purpose input ports after a
reset.
15 PD3
*2
CMOS push-pull
20 BEEP/PE0
19 PE1
General-purpose output ports with shared beep tone output function (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output
port. The b0 and b1 bits are used to select the beep tone frequency. There are two
beep tone frequencies supported.
*: When PE0 is set up as the beep tone output, executing an output instruction to PE0
only changes the state of the internal output latch, it does not affect the beep tone
output in any way. Only the PE0 pin can be switched between the general-purpose
output function and the beep tone output function; the PE1 pin only functions as a
general-purpose output. These pins go to the high-impedance state in backup
mode and remain in that state until an output instruction or a BEEP instruction is
executed. Since these ports are open-drain ports, resistors must be inserted
between these pins and VDD. These ports are set to general-purpose output port
function after a reset.
N-channel open-drain
Continued on next page.
No. 6472-7/14

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관련 데이터시트

부품번호상세설명 및 기능제조사
LC723481W

(LC723481W - LC723483W) Low-Voltage ETR-Controller

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LC723482W

(LC723481W - LC723483W) Low-Voltage ETR-Controller

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