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LC72362N 데이터시트 PDF




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부품번호 LC72362N 기능
기능 Single-Chip PLL Microcontrollers
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LC72362N 데이터시트, 핀배열, 회로
Ordering number : EN5065A
CMOS LSI
LC72358N, 72362N, 72366
Single-Chip PLL Microcontrollers
Overview
The LC72358N, LC72362N, and LC72366 are 1.33 µs
instruction execution time single-chip microcontrollers for
electronic tuning applications. These products incorporate
a high-speed locking circuit and a high-performance direct
PLL circuit that can control the local oscillator C/N
characteristics. These products have 256 or 512 bytes of
RAM and 16K, 24K or 32K bytes of program ROM on
chip, and incorporate a three-channel serial I/O interface,
a six-channel A/D converter and other interfaces.
Features
• ROM
— LC72358N: 8K steps (8191 × 16 bits)
— LC72362N: 12K steps (12287 × 16 bits)
— LC72366: 16K steps (16383 × 16 bits)
The subroutine area in both products is 4K steps
(4095 × 16 bits).
• RAM
— LC72358N, 72362N: 512 × 4 bits (banks 0 to 7)
— LC72366: 1K × 4 bits (banks 0 to F)
• Stack: Eight levels
• Serial I/O: Three channels (8-bit 3-wire format)
There are three internal serial clocks: 12.5 kHz,
37.5 kHz and 187.5 kHz.
• External interrupts:
Two channels (the INT0 and INT1 pins)
Switching between rising and falling edge detection is
supported.
• Internal interrupts:
Three channels
— Two internal timer interrupt channels
The timers provide eight interrupt periods: 100 µs,
1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms.
— One serial I/O interrupt channel
• Multiple interrupt levels:
Four levels
Hardware priority order
INT0 pin > INT1 pin > SI/O pin > internal timer 0 >
internal timer 1
• A/D converter: Six channels (6-bit successive approx-
imation type)
• General-purpose ports
— Input ports: 10
— Output ports: 28
— I/O ports: 25 (These pins can be switched between
input and output in bit units.)
• PLL block
— Built-in sub-charge pump for high-speed locking
— Support for dead zone control
— Built-in unlock detection circuit
— Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50 and 100 kHz
• Universal counter: 20 bits
Supports frequency and period
measurement with counting periods
of 1, 4, 8 and 32 ms.
• Timers: Timer interrupt periods
100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms
and 250 ms
• Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,
3.0 kHz, 3.75 kHz, 4.17 kHz.
• Reset: Built-in voltage detection type reset circuit
• Cycle time: 1.33 µs (all instructions execute in one
cycle)
• Halt mode: The microcontroller operating clock is
stopped in halt mode.
There are four types of event that clear halt
mode: interrupt requests, timer FF
overflows, key inputs, and hold pin inputs.
• Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V
when only the controller
block operates)
• Package: QFP80E (QIP80E)
• OTP version: LC72P366
• Development tools: Emulator .................RE32N
Evaluation chip.......LC72EV350
Evaluation chip board
................................EB-72EV350
This LSI can easily use CCB that is SANYO’s original bus format.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT)/62295TH (OT) No. 5065-1/13




LC72362N pdf, 반도체, 판매, 대치품
LC72358N, 72362N, 72366
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN
VOUT (1)
VOUT (2)
IOUT (1)
IOUT (2)
IOUT (3)
Pd max
Topr
Tstg
Conditions
All input pins
J port
All output ports other than VOUT (1)
J port
D, E, F, G, K, L, M, N, O, P and Q ports,
EO1, EO2, EO3, SUBPD
B and C ports
Ta = –40 to +85°C
Ratings
–0.3 to +6.5
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD + 0.3
0 to 5
0 to 3
0 to 1
400
–40 to +85
–45 to +125
Unit
V
V
V
V
mA
mA
mA
mW
°C
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 3.5 to 5.5 V
Parameter
Supply voltage
Input high level voltage
Input low level voltage
Input frequency
Input amplitude
Input voltage range
Symbol
Conditions
min typ max Unit
VDD (1)
VDD (2)
VDD (3)
VIH (1)
CPU and PLL operating
CPU operating
Memory retention
E, H, I, L, M and Q ports, HCTR and LCTR
(when selected for input)
4.5
3.5
1.3
0.7 VDD
5.0
5.5 V
5.5 V
5.5 V
VDD V
VIH (2)
F, G and K ports, LCTR (period measurement mode),
HOLD
0.8 VDD
VDD V
VIH (3)
VIH (4)
VIL (1)
SNS
A port
E, H, I, L, M and Q ports, HCTR and LCTR
(when selected for input)
2.5
0.6 VDD
0
VDD
VDD
0.3 VDD
V
V
V
VIL (2) A, F, G and K ports, LCTR (period measurement mode)
0
0.2 VDD
V
VIL (3) SNS
0 1.3 V
VIL (4) HOLD
0
0.4 VDD
V
fIN (1)
XIN
4.0 4.5
5.0 MHz
fIN (2)
FMIN: VIN (2), VDD (1)
10 150 MHz
fIN (3)
FMIN: VIN (3), VDD (1)
10 130 MHz
fIN (4)
AMIN (H): VIN (3), VDD (1)
2.0 40 MHz
fIN (5)
AMIN (L): VIN (3), VDD (1)
0.5 10 MHz
fIN (6)
HCTR: VIN (3), VDD (1)
0.4 12 MHz
fIN (7)
LCTR: VIN (3), VDD (1)
100 500 kHz
fIN (8)
LCTR (period measurement): VIH (2), VIL (2), VDD (1)
1
20 × 103
Hz
VIN (1) XIN
0.5 1.5 Vrms
VIN (2) FMIN
0.10
1.5 Vrms
VIN (3) FMIN, AMIN, HCTR, LCTR
0.07
1.5 Vrms
VIN (4) ADI0 to ADI5
0 VDD V
No. 5065-4/13

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LC72362N 전자부품, 판매, 대치품
LC72358N, 72362N, 72366
Continued from preceding page.
Pin No.
76
73
31
Symbol
VSS
VDD
VDD
I/O
——
I/O type
Power supply connections
Function
75 FMIN I Input
FM VCO (local oscillator) input
This pin is selected by the PLL instruction CW1 (b1, b0 are ignored).
Capacitor coupling must be used for signal input.
Input is disabled when the HOLD pin is set low in the hold enable state.
Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state.
74 AMIN I Input
72
SUBPD
O CMOS tristate
AM VCO (local oscillator) input
This pin is selected and the band set by the PLL instruction CW1 (b1, b0).
b1 b0
Band
1 0 2 to 40 MHz (SW)
1 1 0.5 to 10 MHz (MW, LW)
Capacitor coupling must be used for signal input.
Input is disabled when the HOLD pin is set low in the hold enable state.
Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state.
Sub-charge pump output
This pin, in combination with the main charge pump, allows the construction of a high-
speed locking circuit.
The DZC instruction controls the sub-charge pump.
b3 b2
Operation
0 0 High impedance
0 1 Only operates in the unlocked state (450 kHz)
1 0 Only operates in the unlocked state (900 kHz)
1 1 Normal operation
This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable
state.
This pin goes to the high-impedance state in clock stop mode, during the power-on reset,
and in the PLL stop state.
71
EO3
O CMOS tristate
Second PLL charge pump output
This pin outputs a low level when the frequency generated by dividing the local oscillator
signal frequency by N is higher than the reference frequency, and a high level when that
frequency is lower.
This pin goes to the high-impedance state when the frequencies match. (Note that this
pin’s output logic is the opposite of that of the EO1 and EO2 pins.)
This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable
state.
This pin goes to the high-impedance state in clock stop mode, during the power-on reset,
and in the PLL stop state.
Continued on next page.
No. 5065-7/13

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LC72362N

Single-Chip PLL Microcontrollers

Sanyo Semicon Device
Sanyo Semicon Device

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