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PDF LC723756 Data sheet ( Hoja de datos )
| Número de pieza | LC723756 | |
| Descripción | ETR Microcontrollers | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN5931
CMOS IC
LC723732/40/48/56/64
ETR Microcontrollers
Overview
The LC723700 Series are large-capacity ETR
microcontrollers that achieve an instruction execution time
of 1.33 µs and provide up to 64 KB of ROM and up to
2 KB of RAM. They include an on-chip high-performance
PLL circuit that features an added high-speed lock circuit
and can control the C/N characteristics of a local
oscillator. They also provide a rich set of on-chip interface
circuits, including a 3-channel serial I/O port, and an 8-
input 8-bit A/D converter.
Functions
• ROM
— Up to 32K steps (32,767 × 16 bits)
— The subroutine area holds 4 K steps (4,096 × 16 bits)
• RAM
— Up to 4 K × 4 bits (In banks 00 through 3F)
LC723732 – ROM: 32 KB, RAM 1 KB
LC723740 – ROM: 40 KB, RAM 2 KB
LC723748 – ROM: 48 KB, RAM 2 KB
LC723756 – ROM: 56 KB, RAM 2 KB
LC723764 – ROM: 64 KB, RAM 2 KB
• Stack
— 32 levels
• Serial I/O
— Three channels. These circuits can support both 2-
wire and 3-wire 8-bit communication techniques,
and can be switched between MSB first and LSB
first operation.
— One of six internally generated serial transfer clock
rates can be selected: 12.5, 37.5, 187.5, 281.25, 375,
and 450 kHz.
• External interrupts
— Seven interrupt inputs (pins INT0 through INT5, and
the HOLD pin)
These interrupts can be set to switch between rising
and falling edges, although the HOLD pin only
supports falling edge detection.
• Internal interrupts
— Seven interrupts; four internal timer interrupts, and
three serial I/O interrupts.
• Interrupt nesting levels
— 16 levels
— Interrupt are prioritized in hardware as follows:
HOLD pin > INT0 pin > INT1 pin > INT2 pin >
INT3 pin > INT4 pin > INT5 pin > S-I/O0 > S-I/O1
> S-I/O2 > internal TMR0 > internal TMR1 >
internal TMR2 > internal TMR3
• A/D converter
— 8-bit resolution and 8 inputs
• General-purpose ports
— Input ports: 12
— Output ports : 4
— I/O ports: 62 (These pins can be switched between
input and output in 1-bit units.)
• PLL block
— Includes a sub-charge pump for high-speed locking.
— Supports dead zone control.
— Built-in unlock detection circuit.
— Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50, and 100 kHz.
— A second PLL circuit is also included for use in AM
up conversion.
• Universal counter
— This 20-bit counter can be used for either frequency
or period measurement and supports four
measurement (calculation) periods: 1, 4, 8, and 32 ms.
• Timers
— Two fixed timers and two programmable timers (8-
bit counters)
TMR0: Supports four periods: 10 µs, 100 µs, 1 ms,
and 5 ms
TMR1: Supports four periods: 10 µs, 100 µs, 1 ms,
and 10 ms
TMR2 and TMR3: Programmable 8-bit counters.
Input clocks with 10 µs, 100 µs, and 1 ms periods
are provided.
— One 125-ms timer flip-flop provided.
• Beep circuit
— Provides 12 fixed beep tones: 0.5, 1, 2, 2.08, 2.2,
2.5, 3.33, 3.75, 4.17, and 7.03 kHz.
— Programmable 8-bit beep tone generator. Reference
clocks with frequencies of 5 kHz, 15 kHz, and 50
kHz are provided.
• Reset
— Built-in voltage detection reset circuit
— External reset pin
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51398RM (OT) No.5931-1/14
1 page  
LC723732/40/48/56/64
Specifications
Electrical Characteristics
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
IOUT1
IOUT2
Pd max
Topg
Tstg
Conditions
PC-PORT
All input pins other than VIN1
PC, PJ-PORT
All output pins other than VOUT1
PC, PJ-PORT
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
PS, PT, PT-PORT, EO1, EO2, EO3, SUBPD
Ta = –40 to +85°C
Ratings
–0.3 to +6.5
–0.3 to +15
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD + 0.3
0 to +5
0 to +3
400
–40 to +85
–45 to +125
Unit
V
V
V
V
V
mA
mA
mW
°C
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 3.5 to 5.5 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Input frequency
Input amplitude
Input voltage range
Symbol
VDD1
VDD2
VDD3
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
fIN1
fIN2
fIN3
fIN4
fIN5
fIN6
fIN7
fIN8
VIN1
VIN2
VIN3
VIN4
Conditions
CPU and PLL operating
CPU operating
Memory retention
PB, PC, PH, PI, PL, PM, PN, PO, PP, PQ, PR,
PS, PT-PORT, HCTR, LCTR, E03, SUBPD
(with the I/O ports set to input mode.)
PD, PE, PF, PG, PK-PORT, LCTR,
(in period measurement mode), HOLD, RESET
SNS
PA-PORT
PB, PC, PH, PI, PL, PM, PN, PO, PP, PQ, PR,
PS, PT-PORT, HCTR, LCTR, E03, SUBPD
(with the I/O ports set to input mode.)
PA, PD, PE, PF, PG, PK-PORT, LCTR
(in period measurement mode), RESET
SNS
HOLD
XIN
FMIN VIN2, VDD1
FMIN VIN3, VDD1
AMIN(H) VIN3, VDD1
AMIN(L) VIN3, VDD1
HCTR VIN3, VDD1
LCTR VIN3, VDD1
LCTR(period measurement)
VIH2, VIL2, VDD1
XIN
FMIN
FMIN, AMIN, HCTR, LCTR
ADI0 to ADI7
min
4.5
3.5
1.3
0.7 VDD
0.8 VDD
2.5
0.6 VDD
0
0
0
0
4.0
10
10
2.0
0.5
0.4
100
1
0.5
0.07
0.04
0
Ratings
typ
5.0
max
5.5
5.5
5.5
Unit
V
V
V
VDD
V
VDD
VDD
VDD
0.3 VDD
V
V
V
V
0.2 VDD
V
1.3 V
0.4 VDD
V
4.5 5.0 MHz
150 MHz
130 MHz
40 MHz
10 MHz
12 MHz
500 kHz
20 × 103
Hz
1.5 Vrms
1.5 Vrms
1.5 Vrms
VDD
V
No. 5931-5/14
5 Page 
LC723732/40/48/56/64
Continued from preceding page.
Pin No. Symbol
PL0 to 3
68 to 61
PN0 to 3
60 PN0/BEEP
59 PN1
58 PN2
57 PN3
56 to 49
P00 to 3
PP0 to 3
I/O Function
General-purpose I/O ports
I/O
The mode is switched between input and output with the IOS instruction.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
General-purpose I/O port and beep tone output shared function ports
The IOS2 instruction is used to switch between the general-purpose I/O port and the
beep tone output functions.
• When used as a general-purpose input ports:
The general-purpose I/O port function is set up with the IOS2 instruction.
(Pins PN1 through PN3 are general-purpose I/O pins.)
I/O • When used as the beep tone output pin:
The beep tone output function is set up with the IOS2 instruction.
The frequency is set with the BEEP instruction.
When this pin is used as the beep tone output pin, executing an output instruction
for this pin only sets the internal latch and has no influence on the output.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
General-purpose I/O ports
I/O
The mode is switched between input and output with the IOS instruction.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
48 to 41
38 to 33
PQ0 to 3
PR0 to 3
PS0 to 3
PT0 to 1
General-purpose I/O ports
The mode is switched between input and output with the IOS instruction, and data is
I/O
input with the INR instruction and output with the OUTR instruction.
The SPB, RPB, TPT, and TPF instruction cannot be used with these ports.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
99 TEST1
2 TEST2
IC test pins
These pins must be tied to ground.
Equivalent circuit
No. 5931-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LC723756.PDF ] | |
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