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LC72700 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC72700은 전자 산업 및 응용 분야에서
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부품번호 LC72700 기능
기능 Mobile FM Multiplex Broadcast Receiver LSI
제조업체 Sanyo Semicon Device
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LC72700 데이터시트, 핀배열, 회로
Ordering number : EN4870E
CMOS LSI
LC72700E, LC72700G
Mobile FM Multiplex Broadcast Receiver LSI
Overview
The LC72700E and LC72700G are data decoder LSIs for
receiving DARCTM mobile FM multiplex broadcasts. A
multi-function, compact, adjustment-free system can be
implemented in two chips by combining this LSI with the
LV3400M band-pass filter IC, which extracts the
multiplex components from a composite FM signal.
Functions and Features
• Delay detection scheme using a 1T delay
• Built-in error correction function using a 2T delay
• Digital PLL clock regeneration
• Block and frame synchronization detection with a
settable synchronization protection count
• Settable block identifier code (BIC) detection precision
• Error correction using (272,190) codes
• Built-in frame memory for product codes
• Support for both serial and parallel data I/O
• Package
LC72700E: QFP48E
LC72700G: QFP48G
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Package Dimensions
unit: mm
3156-QFP48E
[LC72700E]
unit: mm
3229-QFP48G
[LC72700G]
SANYO: QFP48E
SANYO: QFP48G
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
IOUT
Pd max
Topr
Tstg
Conditions
VDD
CL, CE, and DI pins
Input pins other than VIN1
DO pin
Output pins other than VOUT1
BCLOCK, FCLOCK, and DO pins
Ta 85°C
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to +7.0
–0.3 to VDD + 0.3
0 to 4.0
400
–40 to +85
–55 to +125
Unit
V
V
V
V
V
mA
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63097HA (OT)/D3095HA (OT)/D1594TH (OT) No.4870-1/14




LC72700 pdf, 반도체, 판매, 대치품
LC72700E, LC72700G
Pin Descriptions
Pin No.
3
29
30
31
44
8
9
37
38
39
40
Symbol
MSK
CL
CE
DI
RST
TEST1
TEST2
PST
PORT0
PORT1
PORT2
42 S/P
Function
76 kHz MSK signal input
CCB serial interface
Clock input
Data control input
Data input
System reset input pin (negative logic)
Test pin 1 (normally connected to ground)
Test pin 2 (normally connected to ground)
Parallel IF mode data settings
Port address 0
Port address 1
Port address 2
Serial/parallel IF switch
(Serial mode when high)
25 RE Parallel IF mode data output control signal input
I/O
Input
Input
Input
1
FILCK
Reference clock output for the LV3400M
5
CLK
Clock regeneration monitor output
6
DATA
Demodulated data monitor output
21
BCLOCK
Outputs a high level during block synchronization
22
FCLOCK
Outputs a high level during frame synchronization
23
BL-CK
Block start signal output
24
FC-CK
Frame start signal output
26
RDY
Parallel IF data output enable signal
27
RDY0
Parallel IF data output enable signal
35
INT-R
Output data external CPU interrupt signal
13
DAT0
Parallel IF data output pin 0
14
DAT1
Parallel IF data output pin 1
15
DAT2
Parallel IF data output pin 2
16
DAT3
Parallel IF data output pin 3
17
DAT4
Parallel IF data output pin 4
18
DAT5
Parallel IF data output pin 5
19
DAT6
Parallel IF data output pin 6
20
DAT7
Parallel IF data output pin 7
Output
I/O
32 DO CCB serial interface data output
Output
46 XIN
System clock oscillator crystal connection
47 XOUT
2, 34, 43
VDD Power supply (+4.5 to +5.5 V)
36, 45, 48 VSS Ground pin
4, 7, 10
11, 12, 28 NC Not connected
33, 41
Input
Output
I/O Circuit
A02414
No. 4870-4/14

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LC72700 전자부품, 판매, 대치품
LC72700E, LC72700G
Structure of the Output Data
1. The output data consists of a total of 288 bits (36 bytes). The first two bytes are status information.
2. CNT1 and CNT2 are both output LSB first.
3. Corrected data is output in order starting with the first bit in each block.
4. The BIC code is not output.
5. These points hold for both serial and parallel mode.
*: The CPU can easily select data by first checking the content of the status information when data is read out. Data that
is not required does not have to be read; rather, the CPU can cancel the remainder of the readout operation. (The
CPU can simply ignore data until the next interrupt.)
288 bits (36 bytes)
Corrected data
272 bits (34 bytes)
*Bits 0 and 1 are unused and contain invalid data.
First block data output (Only when VH is low.)
However, this bit is only valid when only horizontal correction is applied, i.e.
when VH = 0.
Normal data
Parity data
Correction OK
Error (uncorrectable data)
Indicates data for which frame synchronization was not achieved
Indicates frame synchronized data
Indicates data for which block synchronization was not achieved
Indicates block synchronized data
Output that was only corrected horizontally (synchronized output)
Output that was vertically corrected
BLN7 to BLN0: Expresses the block number or the parity block number of the output data. The block numbers within a
single frame range from 0 to 189, and the parity block numbers from 0 to 81.
Note that parity block data is not output for vertically corrected data.
No. 4870-7/14

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