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LC72705E 데이터시트 PDF




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부품번호 LC72705E 기능
기능 FM Multiplex Receiver IC for VICS Systems
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LC72705E 데이터시트, 핀배열, 회로
Ordering number : EN5744
CMOS IC
LC72705E
FM Multiplex Receiver IC for VICS Systems
Overview
The LC72705E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. This IC includes a decoder circuit that
performs the required VICS processing, and, in
conjunction with a bandpass filter IC (either the
LV3400M or the LV3403M), can form a compact yet
high-functionality VICS reception system. Note that a
contract with VICS Center is required to evaluate this IC
and to produce end products that support VICS.
Applications
• Receivers for DARC format mobile receiver FM
multiplex broadcasts
unit: mm
3148-QFP44MA
Functions
• MSK delay detection circuit based on a 1T delay
• Error correction function based on a 2T delay (in the
MSK detector stage)
• Digital PLL based Clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Function for setting the number of allowable BIC errors,
the number of synchronization protection states
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2-MHz crystal oscillator circuit
• VICS decoder circuit
Package Dimensions
[LC72705E]
SANYO: QFP44MA
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51198RM (OT) No. 5744-1/14




LC72705E pdf, 반도체, 판매, 대치품
LC72705E
Pin Functions
Pin No. Pin
Function
7 MSK 76-kHz MSK signal input (from the LV3400M/03M)
26
CL CCB serial interface
Clock input
27 CE
Data control input
28 DI
Data input
32 RST System reset input (active low)
30 STNBY Standby mode (active high)
44 TEST Test (Must be connected to ground during normal operation.)
9 TP0
12 TP1
13 TP2
14 TP3
15 TP4
16 TP5
17 TP6 Must be connected to either VDD or VSS.
18 TP7
19 TP8
6 TPC1
8 TPC2
20 TOSEL1
21 TOSEL2
4 FILCK Reference clock output for the LV3400M/03M
10 CLK16 Clock regeneration monitor
11 DATA Demodulated data monitor
23 BLOCK Outputs a high level during block synchronization.
22 FLOCK Outputs a high level during frame synchronization.
24 CRC4 Layer 4 CRCC check result output
25 INT External CPU interrupt signal
34 IC0
35 IC1
36 IC2
37 IC3
Internal connections. These pins must be left open.
39 IC4
41 IC5
42 IC6
43 IC7
29 DO Data output used by the CCB serial interface
I/O
Input
Circuit type
Input
Output
Output
1 XIN
System clock generation crystal oscillator element connections
2 XOUT
5, 31, 38 VDD Power supply (+2.7 to 5.5 V)
3, 33,40 VSS Ground
Input
Output
No. 5744-4/14

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LC72705E 전자부품, 판매, 대치품
LC72705E
• Frame synchronization error protection count
This IC detects the four unique BIC inflection points that exist in a single frame, and increments or decrements the
protection counter depending on whether or not the IC internal frame synchronization counter matches. The data values
are set in the same way as those for the block synchronization protection count are set, namely data in which 1 has been
subtracted from the desired protection count must be transferred. The frame synchronization default values are 8 for
forward protection and 2 for backward protection.
• Control registers
These registers are used to set the IC operating mode. These are described later.
• Notes
— The address bits DI12 to DI15 are ignored.
— Addresses other than those listed above (for example location 0110) are special addresses used for test mode and
other special IC functions. Do not set these locations.
— The default values are the values reloaded into the internal registers when a reset signal (RST) is received. These
values are the recommended values for normal operation, and normally do not need to be modified. If only the
default values are used, there is no need to provide data transfer routines in the external CPU or microcontroller.
Received data
Synchronization
counter BIC position
Reset
Note: *Both forward and backward protection counts are 3.
Figure 1 Block Synchronization Protection Operation (forward backward forward)
Layer 4 CRC Check Circuit
This is a function provided for data group error detection, i.e. layer 4 CRC. After the stipulated number of bytes of data
group data and a 16-bit CRC error check word are transferred, the CRC4 pin outputs a high level if there were no errors.
The CRC4 pin outputs a high level if all the bits in the IC internal CRC check register were 0. When using this function
to perform the layer 4 CRC check, the IC internal CRC check register must be initialized before a single data group data
unit is transferred. This register is initialized by sending bit 7 of the control register. Note that since this flag is not
automatically reset to 0, the application must return it to 0 before transferring layer 4 CRC check data. If there were no
errors in any of the received data groups, the CRC register will always be all zeros after the CRC check of a single data
group. Therefore, the above control register initialization will not be necessary as long as there are no errors in the layer 4
CRC. The data length of the transferred data group data is in units of 8 bits. Also note that while there is no upper limit
on the amount of data transferred in a single operation, data transfers may also be divided into multiple transfer
operations.
No. 5744-7/14

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관련 데이터시트

부품번호상세설명 및 기능제조사
LC72705

FM Multiplex Receiver IC for VICS Systems

Sanyo Semicon Device
Sanyo Semicon Device
LC72705E

FM Multiplex Receiver IC for VICS Systems

Sanyo Semicon Device
Sanyo Semicon Device

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