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LC72706 데이터시트 PDF




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부품번호 LC72706 기능
기능 FM Multiplex Receiver IC Supporting All Worldwide Standards
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LC72706 데이터시트, 핀배열, 회로
Ordering number : EN5745
CMOS IC
LC72706E
FM Multiplex Receiver IC Supporting
All Worldwide Standards
Overview
The LC72706E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. In conjunction with a bandpass filter IC
(either the LV3400M or the LV3403M), the LC72706E
can form a compact yet high-functionality FM multiplex
reception system. This IC supports all the FM multiplex
frame structures (methods A, B, and C) in the ITU-R
recommendations.
Applications
• Receivers for DARC format mobile receiver FM
multiplex broadcasts
Package Dimensions
unit: mm
3148-QFP44MA
[LC72706E]
Functions
• MSK delay detection circuit based on a 1T delay
• Error correction function based on a 2T delay (in the
MSK detector stage)
• Digital PLL based clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Serial control data transfer based support for the A, B,
and C FM multiplex frame structures
• Function for setting the number of allowable BIC errors,
the number of synchronization protection.
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2-MHz crystal oscillator circuit
SANYO: QFP44MA
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40698RM (OT) No. 5745-1/15




LC72706 pdf, 반도체, 판매, 대치품
LC72706E
Pin Functions
Pin No.
7
26
27
28
32
30
44
9
12
13
14
15
16
17
18
19
6
8
20
21
4
10
11
23
22
24
25
34
35
36
37
39
41
42
43
Pin Name
MSK
CL
CE
DI
RST
STNBY
TEST
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TPC1
TPC2
TOSEL1
TOSEL2
FLICK
CLK16
DATA
BLOCK
FLOCK
CRC4
INT
IC0
IC1
IC2
IC3
IC4
IC5
IC6
IC7
Function
76-kHz MSK signal input (from the LV3400M/03M)
CCB serial interface
Clock input
Data control input
Data input
System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)
Must be connected to either VDD or VSS.
Reference clock output for the LV3400M/03M
Clock regeneration monitor
Demodulated data monitor
Outputs a high level during block synchronization.
Outputs a high level during frame synchronization.
Layer 4 CRCC check result output
External CPU interrupt signal
Internal connections. These pins must be left open.
29 DO Data output used by the CCB serial interface
I/O
Input
Input
Output
Output
Circuit type
1 XIN
System clock generation crystal oscillator element connections
2 XOUT
5, 31, 38 VDD Power supply (+2.7 to 5.5 V)
3, 33, 40 VSS Ground
Input
Output
No. 5745-4/15

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LC72706 전자부품, 판매, 대치품
LC72706E
e.g. to a value of 3 or more as opposed to the default of 2, if the block synchronization recognition output (the
BLOCK pin, pin 23) is used to recognize the presence or absence of FM multiplex data.
• Frame Synchronization Error Protection Count
This IC detects the four unique BIC inflection points that exist in a single frame, and increments or decrements the
protection counter depending on whether or not the IC internal frame synchronization counter matches. The data values
are set in the same way as those for the block synchronization protection count are set, namely data in which 1 has been
subtracted from the desired protection count must be transferred. The frame synchronization default values are 8 for
forward protection and 2 for backward protection.
• Control Registers
These registers are used to set the IC operating mode. These are described later.
• Notes
— The address bits DI12 to DI15 are ignored.
— Addresses other than those listed above (for example location 0110) are special addresses used for test mode and
other special IC functions. Do not set these locations.
— The default values are the values reloaded into the internal registers when a reset signal (RST) is received. These
values are the recommended values for normal operation, and normally do not need to be modified. If only the
default values are used, there is no need to provide data transfer routines in the external CPU or microcontroller.
Received data
Synchronization
counter BIC position
*: Both forward and backward protection counts are 3.
Figure 1 Block Synchronization Protection Operation
(forward backward forward)
Layer 4 CRC Check Circuit
This is a function provided for data group error detection, i.e. layer 4 CRC. After the stipulated number of bytes of data
group data and a 16-bit CRC error check word are transferred, the CRC4 pin outputs a high level if there were no errors.
The CRC4 pin outputs a high level if all the bits in the IC internal CRC check register were 0. When using this function
to perform the layer 4 CRC check, the IC internal CRC check register must be initialized before a single data group data
unit is transferred. This register is initialized by sending bit 7 of the control register. Note that since this flag is not
automatically reset to 0, the application must return it to 0 before transferring layer 4 CRC check data. If there were no
errors in any of the received data groups, the CRC register will always be all zeros after the CRC check of a single data
group. Therefore, the above control register initialization will not be necessary as long as there are no errors in the layer 4
CRC. The data length of the transferred data group data is in unit of 8 bits. Also note that while there is no upper limit on
the amount of data transferred in a single operation, data transfers can also be divided into multiple transfer operations.
No. 5745-7/15

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