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ADP1829 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP1829은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADP1829 기능
기능 Step-Down DC-to-DC Controller
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ADP1829 데이터시트, 핀배열, 회로
Dual, Interleavewwdw,.DSatatSehepet-4UD.coomwn
DC-to-DC Controller with Tracking
ADP1829
FEATURES
Fixed frequency operation: 300 kHz, 600 kHz, or
synchronized operation up to 1 MHz
Supply input range: 3.0 V to 18 V
Wide power stage input range: 1 V to 24 V
Interleaved operation results in smaller, low cost
input capacitor
All-N-channel MOSFET design for low cost
±0.85% accuracy at 0°C to 70°C
Soft start, thermal overload, current-limit protection
10 μA shutdown supply current
Internal linear regulator
Lossless RDSON current-limit sensing
Reverse current protection during soft start for handling
precharged outputs
Independent Power OK outputs
Voltage tracking for sequencing or DDR termination
Available in 5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
Telecommunications and networking systems
Medical imaging systems
Base station power
Set-top boxes
Printers
DDR termination
GENERAL DESCRIPTION
The ADP1829 is a versatile, dual, interleaved, synchronous
PWM buck controller that generates two independent output
rails from an input of 3.0 V to 18 V, with power input voltage
ranging from 1.0 V to 24 V. Each controller can be configured
to provide output voltages from 0.6 V to 85% of the input
voltage and is sized to handle large MOSFETs for point-of-load
regulators. The two channels operate 180° out of phase,
reducing stress on the input capacitor and allowing smaller, low
cost components. The ADP1829 is ideal for a wide range of
high power applications, such as DSP and processor core I/O
power, and general-purpose power in telecommunications,
medical imaging, PC, gaming, and industrial applications.
The ADP1829 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, minimizing external
component size and cost. For noise-sensitive applications, it can
also be synchronized to an external clock to achieve switching
TYPICAL APPLICATION CIRCUIT
VIN = 12V
180µF
1µF
PV IN
TRK1
TRK2
VREG
EN1
EN2
180µF
IRLR7807Z
0.47µF
1.2V,
6A
560µF
2.2µH
2k
2k
IRFR3709Z
BST1 BST2
0.47µF
DH1
DH2
ADP1829
SW1
SW2
CSL1
DL1
CSL2
DL2
PGND2
2k
IRFR3709Z
IRLR7807Z
2.2µH
2k
1.8V,
8A
560µF
390pF
2k
4.53k3900pF
PGND1 FB2
FB1 COMP2
COMP1
FREQ
LDOSD
GND SYNC
390pF
1k
3900pF 4.53k
Figure 1.
frequencies between 300 kHz and 1 MHz. The ADP1829
includes soft start protection to prevent inrush current from the
input supply during startup, reverse current protection during
soft start for precharged outputs, as well as a unique adjustable
lossless current-limit scheme utilizing external MOSFET sensing.
For applications requiring power supply sequencing, the
ADP1829 also provides tracking inputs that allow the output
voltages to track during startup, shutdown, and faults. This
feature can also be used to implement DDR memory bus
termination.
The ADP1829 is specified over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.




ADP1829 pdf, 반도체, 판매, 대치품
ADP1829
www.DataSheet4U.com
Parameter
OSCILLATOR
Oscillator Frequency
SYNC Synchronization Range2
SYNC Minimum Input Pulse Width
CURRENT SENSE
CSL1, CSL2 Threshold Voltage
CSL1, CSL2 Output Current
Current Sense Blanking Period
GATE DRIVERS
DH1, DH2 Rise Time
DH1, DH2 Fall Time
DL1, DL2 Rise Time
DL1, DL2 Fall Time
DH to DL, DL to DH Dead Time
LOGIC THRESHOLDS
SYNC, FREQ, LDOSD Input High Voltage
SYNC, FREQ, LDOSD Input Low Voltage
SYNC, FREQ Input Leakage Current
LDOSD Pull-Down Resistance
EN1, EN2 Input High Voltage
EN1, EN2 Input Low Voltage
EN1, EN2 Current Source
EN1, EN2 Input Impedance to 5 V Zener
THERMAL SHUTDOWN
Thermal Shutdown Threshold3
Thermal Shutdown Hysteresis3
POWER GOOD
FB1, UV2 Overvoltage Threshold
FB1, UV2 Overvoltage Hysteresis
FB1, UV2 Undervoltage Threshold
FB1, UV2 Undervoltage Hysteresis
POK1, POK2 Propagation Delay
POK1, POK2 Off Leakage Current
POK1, POK2 Output Low Voltage
UV2 Input Bias Current
Conditions
SYNC = FREQ = GND (fSW = fOSC)
SYNC = GND, FREQ = VREG (fSW = fOSC)
FREQ = GND, SYNC = 600 kHz to 1.2 MHz (fSW = fSYNC/2)
FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (fSW = fSYNC/2)
Relative to PGND
CSL1, CSL2 = PGND
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
SYNC, FREQ = 0 V to 5.5 V
IN = 3.0 V to 18 V
IN = 3.0 V to 18 V
EN1, EN2 = 0 V to 3.0 V
EN1, EN2 = 5.5 V to 18 V
VFB1, VUV2 rising
VFB1, VUV2 rising
VPOK1, VPOK2 = 5.5 V
IPOK1, IPOK2 = 10 mA
Min Typ Max Unit
240 300
480 600
300
600
370
720
600
1000
200
kHz
kHz
kHz
kHz
ns
−30 0
44 50
100
+30 mV
56 μA
ns
15 ns
10 ns
15 ns
10 ns
40 ns
2.2
100
2.0
−0.3 −0.6
100
V
0.4 V
1 μA
V
0.8 V
−1.5 μA
145 °C
15 °C
750 mV
50 mV
550 mV
50 mV
8 μs
1 μA
150 500 mV
10 100 nA
1 Not recommended to use the LDO in dropout when VIN < 5.5 V because of the dropout voltage. Connect IN to VREG when VIN < 5.5 V.
2 SYNC input frequency is 2× single-channel switching frequency. The SYNC frequency is divided by 2 and the separate phases were used to clock the controllers.
3 Guaranteed by design and not subject to production test.
Rev. 0 | Page 4 of 32

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ADP1829 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1829www.DataSheet4U.com
FB1 1
SYNC 2
FREQ 3
GND 4
UV2 5
FB2 6
COMP2 7
TRK2 8
PIN 1
INDICATOR
ADP1829
TOP VIEW
(Not to Scale)
24 POK1
23 BST1
22 DH1
21 SW1
20 CSL1
19 PGND1
18 DL1
17 PV
Figure 3. ADP1829 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1 FB1 Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie
the tap to FB1 to set the output voltage.
2
SYNC
Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz
and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.
3
FREQ
Frequency Select Input. Low for 300 kHz or high for 600 kHz.
4 GND Ground. Connect to a ground plane directly beneath the ADP1829. Tie the bottom of the feedback dividers to
this GND.
5 UV2 Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2
directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.
6 FB2 Voltage Feedback Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB2 to set the output voltage.
7
COMP2
Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.
8
TRK2
Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider from the master
voltage. If the tracking function is not used, connect TRK2 to VREG.
9 SS2 Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.
10
POK2
Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up
resistor from POK2 to VREG.
11
BST2
Boost Capacitor Input for Channel 2. Powers the high-side gate driver DH2. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.
12 DH2 High-Side (Switch) Gate Driver Output for Channel 2.
13 SW2 Switch Node Connection for Channel 2.
14
CSL2
Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set the
current-limit offset.
15
PGND2
Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1829.
16 DL2 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.
17 PV Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground with
a 1 μF capacitor.
18 DL1 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.
19
PGND1
Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1829.
20
CSL1
Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set the
current-limit offset.
21 SW1 Switch Node Connection for Channel 1.
22 DH1 High-Side (Switch) Gate Driver Output for Channel 1.
23
BST1
Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
24
POK1
Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up
resistor from POK1 to VREG.
Rev. 0 | Page 7 of 32

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