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부품번호 | ZL2004 기능 |
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기능 | Adaptive Digital DC-DC Controller | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 30 페이지수
Data Sheet
ZL2004
www.DataSheet4U.com
February 18, 2009
FN6846.0
Adaptive Digital DC-DC Controller with Current Sharing
Description
The ZL2004 is a digital DC-DC controller designed to
work with the ZL1505 MOSFET driver IC. Current
sharing allows multiple devices to be connected in
parallel to source loads with very high current
demands. Adaptive performance optimization
algorithms improve power conversion efficiency across
the entire load range. Zilker Labs Digital-DC™
technology enables a blend of power conversion
performance and power management features.
The ZL2004 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 4.5 V input to a multi-phase supply operating
from a 12V input. The ZL2004 eliminates the need for
complicated power supply managers as well as
numerous external discrete components.
All operating features can be configured by simple pin-
strap/resistor selection or through the SMBus™ serial
interface. The ZL2004 uses the PMBus™ protocol for
communication with a host controller and the Digital-
DC bus for communication between other Zilker Labs
devices.
Features
Power Conversion
• Efficient synchronous buck controller
• Adaptive performance optimization algorithms
• 4.5 V to 14 V input range
• 0.54 V to 4 V output range (with margin)
• ± 1% VOUT set-point accuracy
• Fast load transient response
• Current sharing and phase interleaving
• Digitally adjustable current sense range
• Snapshot™ parameter capture
• RoHS compliant (5 x 5 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Power good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• SMBus communication (PMBus compliant)
• Output voltage and current protection
• Internal non-volatile memory (NVM)
Applications
• Servers / storage equipment
• Telecom / datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
EN PG SS FC ILIM CFG
V25 VR VDD
V (0,1)
VMON
MGN
SYNC
DDC
SCL
SDA
SALRT
POWER
MANAGEMENT
NON-
VOLATILE
MEMORY
I2 C
PWM
CONTROLLER
MONITOR
ADC
LDO
LEVEL
SHIFTER
CURRENT
SENSE
TEMP
SENSOR
PWMH
PWML
ISENA
ISENB
SA (0,1)
VTRK VSEN+/-
XTEMP
SGND DGND
Figure 1. Block Diagram
1 1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
ZL2004
www.DataSheet4U.com
Table 3. Electrical Specifications
VDD = 12 V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C.
Parameter
Conditions
Min Typ Max Unit
Input and Supply Characteristics
IDD supply current at fSW = 200 kHz
IDD supply current at fSW = 1.4 MHz
IDDS shutdown current
VR reference output voltage
V25 reference output voltage
GH no load, GL no load,
MISC_CONFIG[7] = 1
– 16 30 mA
– 25 50 mA
EN = 0 V, No I2C/SMBus activity
–
6.5
8
mA
VDD > 6 V, IVR < 50 mA
4.5 5.2 5.5
V
VR > 3 V, IV25 < 50 mA
2.25 2.5 2.75
V
Output Characteristics
Output voltage adjustment range1
Output voltage set-point resolution
Output voltage accuracy 3
VSEN input bias current
Current sense differential input
voltage (VOUT referenced)
Current sense input bias current
(VOUT referenced, VOUT <= 3.6V)
Soft start delay duration range
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
VIN > VOUT
Set using resistors
Set using I2C/SMBus
Includes line, load, temp
VSEN = 4 V
VISENA - VISENB
ISENA
ISENB
Set using SS pin or resistor
Set using I2C/SMBus
Turn-on delay (precise mode) 4,5
Turn-on delay (normal mode) 6
Turn-off delay 6
Set using SS pin or resistor
Set using I2C
0.6
–
–
-1
–
- 50
-1
- 100
2
0.002
–
–
–
2
0
–
–
10
±0.025
–
80
–
–
–
–
–
±0.25
-0.25/+4
-0.25/+4
–
–
100
3.6
–
–
1
150
50
1
100
20
500
–
–
–
20
200
–
V
mV
% FS2
%
µA
mV
µA
µA
ms
s
ms
ms
ms
ms
ms
µs
Logic Input/Output Characteristics
Logic input bias current
EN,PG,SCL,SDA,SALRT pins - 10 –
10 µA
MGN input bias current
-1 –
1 mA
Logic input low, VIL
Logic input OPEN (N/C)
Multi-mode logic pins
– – 0.8 V
– 1.4 –
V
Logic input high, VIH
2.0 – – V
Logic output low, VOL
IOL ≤ 4 mA
– – 0.4 V
Logic output high, VOH
IOH ≥ -2 mA
2.25 – – V
Notes: 1. Set point adjustment range does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. VOUT set-point measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires approximately 2 ms following an enable signal and prior to ramping its output. The delay accuracy will vary by
±0.25 ms around the 2 ms minimum delay value.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following an assertion of the enable signal (normal mode) or following the de-assertion
of the enable signal.
4 Data Sheet Revision 2/18/2009
www.intersil.com
4페이지 ZL2004
www.DataSheet4U.com
Table 4. Pin Descriptions (continued)
Pin
Label
Type1 Description
20 PWML O PWM Gate low signal.
21 SGND PWR Connect to low impedance ground plane. Internal connection to SGND.
22 PWMH O PWM Gate High signal.
23 VR PWR Internal 5V reference used to power internal drivers.
24
VDD3
PWR Supply voltage.
25 V25 PWR Internal 2.5 V reference used to power internal circuitry.
26
XTEMP
I
External temperature sensor input. Connect to external 2N3904 (Base Emitter
junction).
27 DDC I Single wire DDC bus (Current sharing, inter device communication).
28 MGN I VOUT margin control.
29
CFG
M
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
30 EN I Enable. Active signal enables PWM switching.
31
SS
I, M
Soft start delay and ramp select. Sets the delay from when EN is asserted until the
output voltage starts to ramp and the ramp time.
32 PG O Power good output.
EPAD
SGND
PWR
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
Notes:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. (Refer to page 11).
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
7 Data Sheet Revision 2/18/2009
www.intersil.com
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
ZL2004 | Adaptive Digital DC-DC Controller | Intersil Corporation |
ZL2004-01 | Adaptive Digital DC-DC Controller | Intersil Corporation |
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