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부품번호 | ZL2006 기능 |
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기능 | Adaptive Digital DC-DC Controller | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 45 페이지수
Data Sheet
ZL2006
www.DataSheet4U.com
February 18, 2009
FN6850.0
Adaptive Digital DC-DC Controller with Drivers and Current Sharing
Description
The ZL2006 is a digital DC-DC controller with
integrated MOSFET drivers. Current sharing allows
multiple devices to be connected in parallel to source
loads with very high current demands. Adaptive
performance optimization algorithms improve power
conversion efficiency across the entire load range.
Zilker Labs Digital-DC™ technology enables a blend
of power conversion performance and power
management features.
The ZL2006 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 3.3 V input to a multi-phase supply operating
from a 12 V input. The ZL2006 eliminates the need for
complicated power supply managers as well as
numerous external discrete components.
All operating features can be configured by simple pin-
strap/resistor selection or through the SMBus™ serial
interface. The ZL2006 uses the PMBus™ protocol for
communication with a host controller and the Digital-
DC bus for communication between other Zilker Labs
devices.
Features
Power Conversion
Efficient synchronous buck controller
Adaptive light load efficiency optimization
3 V to 14 V input range
0.54 V to 5.5 V output range (with margin)
±1% output voltage accuracy
Internal 3 A MOSFET drivers
Fast load transient response
Current sharing and phase interleaving
Snapshot™ parameter capture
RoHS compliant (6 x 6 mm) QFN package
Power Management
Digital soft start / stop
Precision delay and ramp-up
Power good / enable
Voltage tracking, sequencing, and margining
Voltage / current / temperature monitoring
I2C/SMBus interface, PMBus compatible
Output voltage and current protection
Internal non-volatile memory (NVM)
Applications
Servers / storage equipment
Telecom / datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
Figure 1. Block Diagram
1
Figure 2. Efficiency vs. Load Current
1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
ZL2006
www.DataSheet4U.com
Table 3. Electrical Specifications
VDD = 12 V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C.
Parameter
Conditions
Min Typ Max
Unit
Input and Supply Characteristics
IDD supply current at fSW = 200 kHz
IDD supply current at fSW = 1.4 MHz
IDDS shutdown current
VR reference output voltage
V25 reference output voltage
GH, GL no load;
MISC_CONFIG[7] = 1
EN = 0 V
No I2C/SMBus activity
VDD > 6 V, IVR < 50 mA
VR > 3 V, IV25 < 50 mA
– 16 30
– 25 50
– 6.5 8
4.5 5.2 5.5
2.25 2.5 2.75
mA
mA
mA
V
V
Output Characteristics
Output voltage adjustment range1
Output voltage set-point resolution
Output voltage accuracy3
VIN > VOUT
Set using resistors
Set using I2C/SMBus
Includes line, load, temp
0.6 – 5.0
– 10 –
– ±0.025 –
-1 –
1
V
mV
% FS2
%
VSEN input bias current
Current sense differential input
voltage (ground referenced)
Current sense differential input
voltage (VOUT referenced)
(VOUT must be less than 4.0 V)
Current sense input bias current
VSEN = 5.5 V
VISENA - VISENB
VISENA - VISENB
Ground referenced
–
- 100
110
–
- 50
- 100
–
–
200
100
50
100
µA
mV
mV
µA
Current sense input bias current
(VOUT referenced, VOUT < 4.0 V)
ISENA
ISENB
-1
- 100
–
–
1
100
µA
µA
Soft start delay duration range4
Set using DLY pin or resistor
Set using I2C/SMBus
2
0.002
–
–
200
500
ms
s
Soft start delay duration accuracy
Turn-on delay (precise mode) 4,5
Turn-on delay (normal mode) 6
Turn-off delay 6
– ±0.25 –
– -0.25/+4 –
– -0.25/+4 –
ms
ms
ms
Soft start ramp duration range
Set using SS pin or resistor 0 – 200
Set using I2C
0 – 200
ms
ms
Soft start ramp duration accuracy
– 100 –
µs
Notes: 1. Does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay
period to approx 2 ms, where in normal mode it may vary up to 4 ms.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following the assertion of the enable signal (normal mode) or following the de-assertion
of the enable signal.
4 Data Sheet Revision 2/18/2009
www.intersil.com
4페이지 2. Pin Descriptions
ZL2006
www.DataSheet4U.com
DGND 1
SYNC 2
SA0 3
SA1 4
ILIM0 5
ILIM1 6
SCL 7
SDA 8
SALRT 9
36-Pin QFN
6 x 6 mm
Exposed Paddle
Connect to SGND
27 VDD
26 BST
25 GH
24 SW
23 PGND
22 GL
21 VR
20 ISENA
19 ISENB
Figure 3. ZL2006 Pin Configurations (top view)
Table 4. Pin Descriptions
Pin Label Type1
1 DGND PWR
2 SYNC I/O,M2
3
4
SA0
SA1
I, M
5
6
ILIM0
ILIM1
I, M
Description
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
Clock synchronization input. Used to set switching frequency of internal clock or for
synchronization to external frequency reference.
Serial address select pins. Used to assign unique SMBus address to each IC or to enable
certain management features.
Current limit select. Sets the overcurrent threshold voltage for ISENA,
ISENB.
7 SCL I/O Serial clock. Connect to external host and/or to other ZL2006s.
8
SDA
I/O Serial data. Connect to external host and/or to other ZL2006s.
9
SALRT
O Serial alert. Connect to external host if desired.
10
11
FC0
FC1
I Loop compensation selection pins.
12
13
V0
V1
I Output voltage selection pins. Used to set VOUT set-point and VOUT max.
14 UVLO I, M Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT.
15 SS I, M Soft start pin. Set the output voltage ramp time during turn-on and turnoff.
16 VTRK I Tracking sense input. Used to track an external voltage source.
17 VSEN+ I Output voltage feedback. Connect to output regulation point.
Notes:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
7 Data Sheet Revision 2/18/2009
www.intersil.com
7페이지 | |||
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