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PDF WM8951L Data sheet ( Hoja de datos )
| Número de pieza | WM8951L | |
| Descripción | Stereo ADC with Microphone Input and Clock Generator | |
| Fabricantes | Wolfson Microelectronics plc | |
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WM8951L
Stereo ADC with Microphone Input and Clock Generator
DESCRIPTION
The WM8951L is a low power stereo ADC with an
integrated microphone interface and crystal oscillator for
clock generation. The WM8951L is ideal for voice recorders,
wireless microphones and games console accessories.
Stereo line and mono microphone level audio inputs are
provided, along with a mute function, programmable line
level volume control and a bias voltage output suitable for
an electret type microphone.
Stereo 24-bit multi-bit sigma delta ADCs are used with
oversampling decimation filters. Digital audio input word
lengths from 16-32 bits and sampling rates from 8kHz to
96kHz are supported.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including
volume controls, mutes and extensive power management
facilities. The device is available in a small 28 lead 5x5mm
quad flat leadless package (QFN).
BLOCK DIAGRAM
FEATURES
• Audio Performance
- ADC SNR 90dB (‘A’ weighted) at 3.3V, 85dB at 1.8V
- Low Power
- 1.42 – 3.6V Digital Supply Operation
- 1.8 – 3.6V Analogue Supply Operation
• Sampling Frequency: 8kHz – 96kHz
• Selectable ADC High Pass Filter
• 2 or 3-Wire MPU Serial Control Interface
• Programmable Audio Data Interface Modes
- I2S, Left, Right Justified or DSP
- 16/20/24/32 bit Word Lengths
- Master or Slave Clocking Mode
• Microphone Input and Electret Bias with Side Tone Mixer
• Available in 5x5mm 28-lead QFN package
APPLICATIONS
• Wireless microphones
• Voice recorders
• Games console accessories
WOLFSON MICROELECTRONICS plc
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Production Data, December 2007 Rev 4.1
Copyright ©2007 Wolfson Microelectronics plc
1 page  
Production Data
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WM8951
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN MAX
Digital supply voltage
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+3.63V
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND1/AGND2 -0.3V
AVDD1/AVDD2 +0.3V
Operating temperature range, TA
-25°C
+85°C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage
(AVDD1/AVDD2).
3. When DBVDD<2.5V, DCVDD must be at least 0.225V lower than DBVDD.
4. When DBVDD ≥2.5V, DVCVDD must be lower than or equal to DBVDD.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital supply range (Core)
DCVDD
1.42 1.5
3.6
V
Digital supply range (Buffer)
DBVDD
1.8 3.6 V
Analogue supply range
AVDD1, AVDD2
1.8 3.6 V
Ground
DGND, AGND1, AGND2
0V
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PD Rev 4.1 December 2007
5
5 Page 
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8951 ADCLRC
ADC
ADCDAT
DSP
ENCODER/
DECODER
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WM8951
Figure 5 Slave Mode Connection
BCLK
ADCLRC
t
BCH
t
BCL
t
BCY
ADCDAT
t
DD
t
LRH
t
LRSU
Figure 6 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
tBCY
tBCH
tBCL
ADCLRC set-up time to
BCLK rising edge
tLRSU
ADCLRC hold time from
BCLK rising edge
tLRH
ADCDAT propagation delay
from BCLK falling edge
tDD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50 ns
20 ns
20 ns
10 ns
10 ns
0 15 ns
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PD Rev 4.1 December 2007
11
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet WM8951L.PDF ] | |
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