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PDF PM73122 Data sheet ( Hoja de datos )
| Número de pieza | PM73122 | |
| Descripción | 32 LINK CES/DBCES AAL1 SAR PROCESSOR | |
| Fabricantes | PMC-Sierra | |
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RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM731w22wwA.ADLa1taGSAhTeOetR4U-3.c2om
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PM73122
AAL1GATOR-32
ATM ADAPTATION LAYER 1
SEGMENTATION AND REASSEMBLY
PROCESSOR-32
DATASHEET
PROPRIETARY AND CONFIDENTIAL
RELEASED
ISSUE 7: JUNE 2001
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
1 page  
RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM731w22wwA.ADLa1taGSAhTeOetR4U-3.c2om
32 LINK CES/DBCES AAL1 SAR PROCESSOR
CONTENTS
1 CHANGES FROM REV. A TO REV. B ..................................................... 1
2 CHANGES FROM REV B TO REV C ...................................................... 2
3 FEATURES .............................................................................................. 3
4 APPLICATIONS ....................................................................................... 9
5 REFERENCES....................................................................................... 10
6 APPLICATION EXAMPLES ....................................................................11
6.1 ATM MULTI-SERVICE SWITCH ..................................................11
6.2 PASSIVE OPTICAL NETWORK (PON) SYSTEM....................... 12
6.3 DIGITAL ACCESS CROSS-CONNECT SYSTEM (DACS) WITH AN
ATM INTERFACE........................................................................ 13
7 BLOCK DIAGRAM ................................................................................. 14
8 DESCRIPTION ...................................................................................... 15
9 PIN DIAGRAM ....................................................................................... 16
10 PIN DESCRIPTION................................................................................ 17
10.1 UTOPIA INTERFACE SIGNALS (52) .......................................... 17
10.2 MICROPROCESSOR INTERFACE SIGNALS (43)..................... 26
10.3 RAM 1 INTERFACE SIGNALS(41) ............................................. 28
10.4 LINE INTERFACE SIGNALS(DIRECT LOW SPEED)(132) ........ 31
10.5 LINE INTERFACE SIGNALS(H-MVIP)(37) ................................. 36
10.6 SBI INTERFACE SIGNALS (ONLY USED IN SBI MODE)(64).... 38
10.7 LINE INTERFACE SIGNALS(HIGH SPEED)(10)........................ 45
10.8 RAM 2 INTERFACE SIGNALS (ONLY USED IN H-MVIP, HS, AND
SBI MODES)(41)......................................................................... 46
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iv
5 Page 
RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM731w22wwA.ADLa1taGSAhTeOetR4U-3.c2om
32 LINK CES/DBCES AAL1 SAR PROCESSOR
LIST OF REGISTERS
REGISTER 0X80000: RESET AND DEVICE ID REGISTER (DEV_ID_REG)253
REGISTER 0X80010, … 13: A1SPN COMMAND REGISTER (AN_CMD_REG)
............................................................................................................. 254
REGISTER 0X80020, … 23 : A1SPN ADD QUEUE FIFO REGISTER
(AN_ADDQ_FIFO) ............................................................................... 256
REGISTER 0X80030, … 33 : A1SPN CLOCK CONFIGURATION REGISTER
(AN_CLK_CFG) ................................................................................... 257
REGISTER 0X80100: RAM CONFIGURATION REGISTER (RAM_CFG_REG)
............................................................................................................. 259
REGISTER 0X80120: UI COMMON CONFIGURATION REGISTER
(UI_COMN_CFG)................................................................................. 261
REGISTER 0X80121: UI SOURCE CONFIG REG (UI_SRC_CFG) ............ 263
REGISTER 0X80122: UI SINK CONFIG REG (UI_SNK_CFG).................... 265
REGISTER 0X80123: SLAVE SOURCE ADDRESS CONFIG REGISTER
(UI_SRC_ADD_CFG) .......................................................................... 267
REGISTER 0X80124: SLAVE SINK ADDRESS CONFIG REGISTER
(UI_SNK_ADD_CFG)........................................................................... 268
REGISTER 0X80125: UI TO UI LOOPBACK VCI (U2U_LOOP_VCI)........... 269
REGISTER 0X80126: UI SOURCE POLLING PRIORITY LIST REGISTER
(UI_SRC_POLL_LIST)......................................................................... 270
REGISTER 0X80200H, 01H … 0FH: LOW SPEED LINE N CONFIGURATION
REGISTERS(LS_LN_CFG_REG)........................................................ 272
REGISTER 0X80210H: LINE MODE REGISTER(LINE_MODE_REG).......... 273
REGISTER 0X80300H: SBI BUS CONFIGURATION
REGISTER(SBI_BUS_CFG_REG)...................................................... 275
REGISTER 0X80301H: SBI LINK CONFIGURATION
REGISTER(SBI_LNK_CFG_REG) ...................................................... 278
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
x
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PM73122.PDF ] | |
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