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PDF LTC1744 Data sheet ( Hoja de datos )
| Número de pieza | LTC1744 | |
| Descripción | 14-Bit 50Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Sample Rate: 50Msps
s 77dB SNR and 87dB SFDR (3.2V Range)
s 73.5dB SNR and 90dB SFDR (2V Range)
s No Missing Codes
s Single 5V Supply
s Power Dissipation: 1.2W
s Selectable Input Ranges: ±1V or ±1.6V
s 150MHz Full Power Bandwidth S/H
s Pin Compatible Family
25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)
50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)
65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)
80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)
s 48-Pin TSSOP Package
U
APPLICATIO S
s Telecommunications
s Receivers
s Base Stations
s Spectrum Analysis
s Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1744www.DataSheet4U.com
14-Bit, 50Msps ADC
DESCRIPTIO
The LTC®1744 is a 50Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. Pin selectable input ranges of±1V and ±1.6V
along with a resistor programmable mode allow the
LTC1744’s input range to be optimized for a wide variety
of applications.
The LTC1744 is perfect for demanding communications
applications with AC performance that includes 77dB
SNR and 87dB spurious free dynamic range. Ultralow jitter
of 0.3psRMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±4LSB
maximum INL and no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
BLOCK DIAGRA
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT AIN–
SENSE
RANGE
SELECT
VCM
4.7µF
2.5VREF
50Msps, 14-Bit ADC with a ±1V Differential Input Range
S/H
CIRCUIT
14-BIT
PIPELINED ADC
CORRECTION
LOGIC AND
14
OUTPUT
SHIFT
LATCHES
REGISTER
OVDD
0.1µF
OF
•••
D13
D0
CLKOUT
OGND
0.5V TO 5V
0.1µF
BUFFER
DIFF AMP
VDD
5V
1µF 1µF 1µF
CONTROL LOGIC
GND
REFLB REFHA
4.7µF
0.1µF
1µF
REFLA REFHB ENC ENC MSBINV
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
1744 BD
OE
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LTC1744www.DataSheet4U.com
TYPICAL PERFOR A CE CHARACTERISTICS (Note 5)
Typical INL, 3.2V Range
2.0
TA = 25°C
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
4000
8000 12000
CODE
16000
1744 G01
Nonaveraged, 8192 Point FFT,
Input Frequency = 20MHz, –1dB,
2V Range
0.5
–10.0 TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G04
Averaged, 8192 Point 2-Tone FFT,
Input Frequency = 2.5MHz and
5.2MHz, 2V Range
0.5
–10.0
TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G07
Typical DNL, 3.2V Range
1.0
TA = 25°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4000
8000 12000
CODE
16000
1744 G02
Nonaveraged, 8192 Point FFT,
Input Frequency = 2.5MHz, –1dB,
3.2V Range
0.5
–10.0
TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G05
Averaged, 8192 Point 2-Tone FFT,
Input Frequency = 2.5MHz and
5.2MHz, 3.2V Range
0.5
–10.0
TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G08
Nonaveraged, 8192 Point FFT,
Input Frequency = 2.5MHz, –1dB,
2V Range
0.5
–10.0
TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G03
Nonaveraged, 8192 Point FFT,
Input Frequency = 20MHz, –1dB,
3.2V Range
0.5 TA = 25°C
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G06
Averaged, 8192 Point FFT, Input
Frequency = 2.5MHz, – 6dB,
2V Range
0.5
–10.0
TA = 25°C
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY (MHz)
25.37
1744 G10
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LTC1744www.DataSheet4U.com
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S / (N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log V22 + V32 + V42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
2, 3, etc. The 3rd order intermodulation products are 2fa
+ fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = – 20log (2π) • FIN • TJITTER
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0, 1,
CONVERTER OPERATION
As shown in Figure 1, the LTC1744 is a CMOS pipelined
multistep converter. The converter has four pipelined
ADC stages; a sampled analog input will result in a
digitized value five cycles later, see the Timing Diagram
section. The analog input is differential for improved
common mode noise immunity and to maximize the input
range. Additionally, the differential input drive will reduce
even order harmonics of the sample-and-hold circuit. The
encode input is also differential for improved common
mode noise immunity.
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC1744.PDF ] | |
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