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부품번호 | 74LVC1G79 기능 |
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기능 | Single D-type flip-flop positive-edge trigger | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 16 페이지수
74LVC1G79
www.DataSheet4U.com
Single D-type flip-flop; positive-edge trigger
Rev. 07 — 29 August 2007
Product data sheet
1. General description
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V)
s ±24 mA output drive (VCC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
s Specified from −40 °C to +125 °C
NXP Semiconductors
74LVC1G79www.DataSheet4U.com
Single D-type flip-flop; positive-edge trigger
7. Functional description
Table 4.
Input
CP
↑
↑
L
Function table[1]
D
L
H
X
Output
Q
L
H
q
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
VI input voltage
IOK output clamping current
VO output voltage
VI < 0 V
VO > VCC or VO < 0 V
Active mode
Power-down mode
−0.5
−50
[1] −0.5
-
[1][2] −0.5
[1][2] −0.5
+6.5
-
+6.5
±50
VCC + 0.5
+6.5
V
mA
V
mA
V
V
IO
ICC
IGND
Ptot
Tstg
output current
supply current
ground current
total power dissipation
storage temperature
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
-
-
−100
[3] -
−65
±50
100
-
250
+150
mA
mA
mA
mW
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74LVC1G79_7
Product data sheet
Rev. 07 — 29 August 2007
© NXP B.V. 2007. All rights reserved.
4 of 16
4페이지 NXP Semiconductors
74LVC1G79w w w . D a t a S h e e t 4 U . c
Single D-type flip-flop; positive-edge trigger
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tpd propagation delay CP to Q; see Figure 7 [2]
VCC = 1.65 V to 1.95 V
1.0 3.6 9.9
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.5 2.3 7.0
0.5 2.6 6.0
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.5 2.2 5.0
0.5 1.7 3.8
tsu set-up time
D to CP; see Figure 8
VCC = 1.65 V to 1.95 V
2.5 1.4
-
VCC = 2.3 V to 2.7 V
1.7 0.9
-
VCC = 2.7 V
1.7 0.9
-
VCC = 3.0 V to 3.6 V
1.3 0.6
-
th hold time
VCC = 4.5 V to 5.5 V
D to CP; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.2 0.6
0
0
+0.5
+0.5
+0.5
−0.7
−0.4
−0.3
−0.3
−0.2
-
-
-
-
-
-
tW pulse width
CP HIGH or LOW;
see Figure 8
VCC = 1.65 V to 1.95 V
3.0 1.1
-
VCC = 2.3 V to 2.7 V
2.5 0.7
-
VCC = 2.7 V
2.5 0.6
-
VCC = 3.0 V to 3.6 V
2.5 0.6
-
fmax maximum
frequency
VCC = 4.5 V to 5.5 V
CP; see Figure 8
VCC = 1.65 V to 1.95 V
2.0 0.5
160 250
-
-
VCC = 2.3 V to 2.7 V
160 300
-
VCC = 2.7 V
160 350
-
VCC = 3.0 V to 3.6 V
160 450
-
VCC = 4.5 V to 5.5 V
CPD power dissipation VI = GND to VCC;
capacitance
VCC = 3.3 V
200
[3] -
500
17
-
-
−40 °C to +125 °C Unit
Min Max
1.0 12.5 ns
0.5 9.0 ns
0.5 8.0 ns
0.5 6.5 ns
0.5 5.0 ns
2.5 - ns
1.7 - ns
1.7 - ns
1.2 - ns
1.2 - ns
0 - ns
0 - ns
0.5 - ns
0.5 - ns
0.5 - ns
3.0 - ns
2.5 - ns
2.5 - ns
2.5 - ns
2.0 - ns
160 - MHz
160 - MHz
160 - MHz
160 - MHz
200 - MHz
- - pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
74LVC1G79_7
Product data sheet
Rev. 07 — 29 August 2007
© NXP B.V. 2007. All rights reserved.
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부품번호 | 상세설명 및 기능 | 제조사 |
74LVC1G74 | Single D-type flip-flop | NXP Semiconductors |
74LVC1G79 | Single D-type flip-flop positive-edge trigger | NXP Semiconductors |
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