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부품번호 | EBE82FF4A1RQ 기능 |
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기능 | 8GB Fully Buffered DIMM | ||
제조업체 | Elpida Memory | ||
로고 | |||
PRELIMINARY DATA SHEET
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8GB Fully Buffered DIMM
EBE82FF4A1RQ
Specifications
• Density: 8GB
• Organization
1024M words × 72 bits, 4 ranks
• Mounting 36 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
DDP: 2 pieces of 1Gb chips sealed in one package
• Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
• Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V +0.075V/ −0.045V
• Data rate: 667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• JEDEC standard Raw Card AA Design
• Industry Standard Advanced Memory Buffer (AMB)
• High-speed differential point-to-point link interface at
1.5V (JEDEC spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
• Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
• Channel error detection and reporting
• Automatic DDR2 SDRAM bus and channel
calibration
• SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
System clock
frequency
167MHz
FB-DIMM
Speed grade
PC2-5300F
Peak channel
throughput
8.0GByte/s
DDR2 SDRAM
FB-DIMM link data rate
4.0Gbps
Speed Grade
DDR data rate
DDR2-667 (5-5-5) 667Mbps
Document No. E1242E20 (Ver. 2.0)
Date Published February 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008
EBE82FF4A1RQ
Advanced Memory Buffer Block Diagram
Southbound
Data in 10×2
Southbound
10×2 Data out
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Reference
clock
1×2
/RESET
SMBus
Data merge
PLL RE-time
Re-synch
Reset
control
Demux
10×12
PISO
10×12
Thermal
sensor
Command
decoder &
CRC check
Core
controller
and CSRs
failover
Link init SM
and control
and CSRs
Init
patterns
IBIST-RX
IBIST-TX
LAI logic
DRAM Command
Write data
FIFO
DDR state controller
and CSRs
External MemBIST
DDR calibration
Mux
4
DRAM clock
4
DRAM clock
Command
out
Mux
Mux Data out
DRAM
interface
24 DRAM
address and
command copy1
24 DRAM
address and
command copy2
A2 for the ECC DRAMs
4 A6 for the ECC DRAMs
DRAM chip select
Data in
72+18×2
DRAM
data and strobes
Data CRC
generator and
Read FIFO
LAI
controller
Mux
Sync & idle
pattern
generator
NB LAI Buffer
IBIST-TX
IBIST-RX
Link init SM
and control
and CSRs
SMBus
controller
failover
14×6×2
PISO
14×12
Re-synch
Demux
Data merge
RE-time
Northbound 14×2
Data Out
14×2 Northbound
Data In
Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.
Preliminary Data Sheet E1242E20 (Ver. 2.0)
4
4페이지 EBE82FF4A1RQ
Block Diagram
VSS
/CS1
/CS3
/CS0
/CS2
DQS0
/DQS0
4
DQ0 to DQ3
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D0
4
DQ0
to DQ3
D36
DQS9
/DQS9
4
DQ4 to DQ7
DM /CS DQS /DQS
DQ0
to DQ3
D1
4
DM /CS DQS /DQS
DQ0
to DQ3
D37
DQS1
/DQS1
DQ8 to DQ11 4
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D2
4
DQ0
to DQ3
D38
DQS10
/DQS10
4
DQ12 to DQ15
DQS2
/DQS2
4
DQ16 to DQ19
DQS11
/DQS11
4
DQ20 to DQ23
DQS3
/DQS3
DQ24 to DQ27 4
DQS12
/DQS12
DQ28 to DQ31 4
DQS8
/DQS8
4
CB0 to CB3
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D3
4
DQ0
to DQ3
D39
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D4
4
DQ0
to DQ3
D40
DM /CS DQS /DQS
DQ0
to DQ3
D5
4
DM /CS DQS /DQS
DQ0
to DQ3
D41
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D6
4
DQ0
to DQ3
D42
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D7
4
DQ0
to DQ3
D43
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
to DQ3
D8
4
DQ0
to DQ3
D44
4
4
4
4
4
4
4
4
4
Block Diagram (1)
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DM /CS DQS /DQS
DQ0
to DQ3
D18
4
DM /CS DQS /DQS
DQ0
to DQ3
D54
DM /CS DQS /DQS
DQ0
to DQ3
D19
4
DM /CS DQS /DQS
DQ0
to DQ3
D55
DM /CS DQS /DQS
DQ0
to DQ3
D20
4
DM /CS DQS /DQS
DQ0
to DQ3
D56
DM /CS DQS /DQS
DQ0
to DQ3
D21
4
DM CS DQS /DQS
DQ0
to DQ3
D57
DM /CS DQS /DQS
DQ0
to DQ3
D22
4
DM /CS DQS /DQS
DQ0
to DQ3
D58
DM /CS DQS /DQS
DQ0
to DQ3
D23
4
DM /CS DQS /DQS
DQ0
to DQ3
D59
DM /CS DQS /DQS
DQ0
to DQ3
D24
4
DM /CS DQS /DQS
DQ0
to DQ3
D60
DM /CS DQS /DQS
DQ0
to DQ3
D25
4
DM /CS DQS /DQS
DQ0
to DQ3
D61
DM /CS DQS /DQS
DQ0
to DQ3
D26
4
DM /CS DQS /DQS
DQ0
to DQ3
D62
Preliminary Data Sheet E1242E20 (Ver. 2.0)
7
7페이지 | |||
구 성 | 총 23 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
EBE82FF4A1RQ | 8GB Fully Buffered DIMM | Elpida Memory |
EBE82FF4A1RR | 8GB Fully Buffered DIMM | Elpida Memory |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |