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PDF EBE82FF4A1RR Data sheet ( Hoja de datos )
| Número de pieza | EBE82FF4A1RR | |
| Descripción | 8GB Fully Buffered DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
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8GB Fully Buffered DIMM
EBE82FF4A1RR
Specifications
• Density: 8GB
• Organization
1024M words × 72 bits, 4 ranks
• Mounting 36 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
DDP: 2 pieces of 1Gb chips sealed in one package
• Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
• Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V +0.075V/ −0.045V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• JEDEC standard Raw Card AA Design
• Industry Standard Advanced Memory Buffer (AMB)
• High-speed differential point-to-point link interface at
1.5V (JEDEC spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
• Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
• Channel error detection and reporting
• Automatic DDR2 SDRAM bus and channel
calibration
• SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
System clock
frequency
200MHz
167MHz
FB-DIMM
Speed grade
PC2-6400F
PC2-5300F
Peak channel
throughput
9.6GByte/s
8.0GByte/s
DDR2 SDRAM
FB-DIMM link data rate
4.8Gbps
4.0Gbps
Speed Grade
DDR2-800 (5-5-5)
DDR2-667 (5-5-5)
DDR data rate
800Mbps
667Mbps
Document No. E1339E20 (Ver. 2.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
1 page  
EBE82FF4A1RR
Interfaces
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Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,
one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or
an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on an FB-DIMM.
Memory Interface
NB FBD
out Link
SB FBD
in Link
AMB
NB FBD
in Link
SB FBD
out Link
SMB
Block Diagram AMB Interfaces
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8
DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven
to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the
next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the
direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives
the data to the next DIMM until the host is reached.
Host
Southbound
Nourthbound
AMB
AMB
AMB
AMB
n/c n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Preliminary Data Sheet E1339E20 (Ver. 2.0)
5
5 Page 
EBE82FF4A1RR
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
AMB core power voltage relative to VSS
DRAM interface power voltage relative to VSS
Termination voltage relative to VSS
Storage temperature
Symbol
VIN/VOUT
VCC
VDD
VTT
Tstg
Value
–0.3 to +1.75
–0.3 to +1.75
–0.5 to +2.30
–0.5 to +2.30
–55 to +100
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Unit Note
V
V
V
V
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Conditions
Parameter
Symbol
Value
Unit Note
SDRAM component case temperature
TC_DRAM
0 to +95
°C 1
AMB component case temperature
TC_AMB
110
°C
Note: 1. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of
EMRS (2) bit A7 is required.
DC Operating Conditions
Parameter
Symbol
min. typ.
max.
Unit Note
AMB supply voltage
VCC
1.455
1.50
1.575
V
DDR2 SDRAM supply voltage VDD
1.7 1.8 1.9
V
Input termination voltage
VTT
0.48 × VDD 0.50 × VDD 0.52 × VDD
V
EEPROM supply voltage
VDDSPD
3.0 3.3 3.6
V
SPD input high voltage
VIH (DC)
2.1 —
VDDSPD
V
1
SPD input low voltage
VIL (DC)
— — 0.8
V1
RESET input high voltage
VIH (DC)
1.0 —
—
V2
RESET input low voltage
VIL (DC)
— — 0.5
V2
Leakage current (RESET)
IL
–90 —
90
µA 2
Leakage current (link)
IL
–5 —
5
µA 3
Notes: 1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal /RESET.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface
specification.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
11
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