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MAX1124 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MAX1124
기능 250Msps Analog-to-Digital Converter
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MAX1124 데이터시트, 핀배열, 회로
19-3029; Rev 1; 2/04
www.DataSheet4U.com
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
General Description
The MAX1124 is a monolithic 10-bit, 250Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1124 achieves a spurious-free dynamic range
(SFDR) of 71dBc. Its excellent signal-to-noise ratio
(SNR) of 57.1dB at 10MHz remains flat (within 1dB) for
input tones up to 500MHz. This makes the MAX1124
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
The MAX1124 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1124 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industri-
al (-40°C to +85°C) temperature range.
For pin-compatible, lower speed versions of the
MAX1124, refer to the MAX1122 (170Msps) and the
MAX1123 (210Msps) data sheets. For a pin-compatible
8-bit version of the MAX1124, refer to the MAX1121
data sheet.
Applications
Wireless and Wired Broadband Communication
Cable-Head End Systems
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Features
250Msps Conversion Rate
SNR = 56.8dB/55.5dB at fIN = 100MHz/500MHz
SFDR = 71dBc/63.8dBc at fIN = 100MHz/500MHz
NPR = 54.8dB at fNOTCH = 28.8MHz
Single 1.8V Supply
477mW Power Dissipation at 250Msps
On-Chip Track-and-Hold and Internal Reference
On-Chip Selectable Divide-by-2 Clock Input
LVDS Digital Outputs with Data Clock Output
Evaluation Kit Available (Order MAX1124EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1124EGK
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
68 QFN-EP*
TOP VIEW
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AVCC 1
AGND 2
REFIO 3
REFADJ 4
AGND 5
AVCC 6
AGND 7
INP 8
INN 9
AGND 10
AVCC
AVCC
AVCC
AVCC
AGND
11
12
13
14
15
AGND 16
CLKDIV 17
EP
MAX1124
51 D6P
50 D6N
49 D5P
48 D5N
47 D4P
46 D4N
45 OGND
44 OVCC
43 DCLKP
42 DCLKN
41 OVCC
40 D3P
39 D3N
38 D2P
37 D2N
36 D1P
35 D1N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.




MAX1124 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. 25°C guar-
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Output Offset Voltage
OVOS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
CONDITIONS
MIN
1.125
TYP
MAX UNITS
1.310
V
Digital Input Voltage Low
VIL
0.2 x
AVCC
V
Digital Input Voltage High
TIMING CHARACTERISTICS
CLK to Data Propagation Delay
CLK to DCLK Propagation Delay
Data Valid to DCLK Rising Edge
LVDS Output Rise-Time
LVDS Output Fall-Time
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 3)
VIH
tPDL
tCPDL
tCPDL -
tPDL
tRISE
tFALL
Figure 4
Figure 4
Figure 4 (Note 2)
20% to 80%, CL = 5pF
20% to 80%, CL = 5pF
tLATENCY
AVCC
OVCC
IAVCC
IOVCC
PDISS
PSRR
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
Offset
Gain
0.8 x
AVCC
V
0.92
1.5
2.85
1.35
460
460
8
1.86
ns
ns
ns
ps
ps
Clock
cycles
1.7 1.8 1.9
V
1.7 1.8 1.9
V
220 290
mA
45 75 mA
477 657
mW
1.6 mV/V
1.9 %FS/V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4 _______________________________________________________________________________________

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MAX1124 전자부품, 판매, 대치품
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100, TA = +25°C.)
SINAD vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
60
59
58
57
56
55
54
53
52
51
50
-40
-15 10 35 60
TEMPERATURE (°C)
85
FS VOLTAGE vs. FS ADJUST RESISTOR
1.34
FIGURE 6
1.32
1.30
RESISTOR VALUE APPLIED
1.28 BETWEEN REFADJ AND AGND
1.26
1.24
1.22
RESISTOR VALUE APPLIED
1.20 BETWEEN REFADJ AND REFIO
1.18
1.16
0 100 200 300 400 500 600 700 800 900 1000
FS ADJUST RESISTOR ()
SFDR vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
80
75
70
65
60
55
50
-40
-15 10 35 60
TEMPERATURE (°C)
85
SNR vs. VOLTAGE SUPPLY
(fIN = 60.0294MHz, AIN = -0.5dBFS)
60
AVCC = OVCC
59
58
57
56
55
54
53
52
51
50
1.5
1.6 1.7 1.8 1.9 2.0
VOLTAGE SUPPLY (V)
2.1
POWER DISSIPATION vs. fSAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
505
495
485
475
465
455
445
435
425
10 50 90 130 170 210 250
fSAMPLE (MHz)
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(fSAMPLE = 250.0057MHz)
1.2350
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
1.2340
1.2330
1.2320
1.2310
1.2300
1.5
1.6 1.7 1.8 1.9 2.0
SUPPLY VOLTAGE (V)
2.1
NOISE HISTOGRAM
(DC INPUT, 128k-POINT DATA RECORD)
8.0E+04
7.0E+04
74401
fSAMPLE = 250MHz
6.0E+04
56333
5.0E+04
4.0E+04
PROPAGATION DELAY TIMES
vs. TEMPERATURE
6
5
4
tCPDL
3
3.0E+04
2.0E+04
1.0E+04
0.0E+00
295
507
43
508 509 510
DIGITAL OUTPUT NOISE
511
2
1
0
-40
tPDL
-15 10 35 60
TEMPERATURE (°C)
85
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