PDF HYS72T64001HP Data sheet ( Hoja de datos )

Número de pieza	HYS72T64001HP
Descripción	240-Pin Registered DDR2 SDRAM Modules
Fabricantes	Qimonda AG
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No Preview Available ! September 2006 www.DataSheet4U.com HYS72T32000HP–[3S/3.7]–A HYS72T64001HP–[3S/3.7]–A HYS72T64020HP–[3S/3.7]–A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Compilant Internet Data Sheet Rev. 1.01 1 page Internet Data Sheet www.DataSheet4U.com HYS72T[32/64]xxxHP–[3S/3.7]–A Registered DDR2 SDRAM Modules 1.2 Description The QIMONDA HYS72T[32/64]xxxHP–[3S/3.7]–A module family are Registered DIMM (RDIMM with parity) with 30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M × 72 (256 Mbyte) and 64M x 72 (512 MByte) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 256-Mbit Double-Data- Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E²PROM device using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. Product Type1) Compliance Code2) TABLE 4 Ordering Information for RoHS Compliant Products Description SDRAM Technology PC2-5300 HYS72T32000HP–3S–A 256MB 1R×8 PC2–5300P–555–12–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HP–3S–A 512MB 1R×4 PC2–5300P–555–12–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HP–3S–A 512MB 2R×8 PC2–5300P–555–12–G0 2 Rank, ECC 256 Mbit (×8) PC2-4200 HYS72T32000HP–3.7–A 256MB 1R×8 PC2–4200P–444–12–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HP–3.7–A 512MB 1R×4 PC2–4200P–444–12–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HP–3.7–A 512MB 2R×8 PC2–4200P–444–12–G0 2 Rank, ECC 256 Mbit (×8) 1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T64020HP–3.7–A, indicating Rev. “A” dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–G0”, where 4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “G” DIMM Density 256 MB 512 MB 512 MB Module Organization 32M × 72 64M × 72 64M × 72 Memory Ranks 1 1 2 ECC/ Non-ECC ECC ECC ECC # of SDRAMs 9 18 18 TABLE 5 Address Format # of row/bank/columns bits Raw Card 13/2/10 13/2/11 13/2/10 F H G Rev. 1.01, 2006-09 03292006-ZZHP-PR83 5 5 Page Ball No. Name Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17 Pin Buffer Function Type Type I/O SSTL Data Strobes 17:0 I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL Internet Data Sheet www.DataSheet4U.com HYS72T[32/64]xxxHP–[3S/3.7]–A Registered DDR2 SDRAM Modules Rev. 1.01, 2006-09 03292006-ZZHP-PR83 11 11 Page

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