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LX128EB 데이터시트 PDF




Lattice Semiconductor에서 제조한 전자 부품 LX128EB은 전자 산업 및 응용 분야에서
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부품번호 LX128EB 기능
기능 High Performance Interfacing and Switching
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LX128EB 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ispGDX2Family
Includes
High-
High Performance Interfacing and Switching
September 2005
Features
Performance,
Low-Cost
“E-Series” Two Options Available
Data Sheet
• High-performance sysHSI (standard part number)
High Performance Bus Switching
• Low-cost, no sysHSI (“E-Series”)
• High bandwidth
– Up to 12.8 Gbps (SERDES)
sysHSI Blocks Provide up to 16 High-speed
– Up to 38 Gbps (without SERDES)
Channels
• Up to 16 (15x10) FIFOs for data buffering
• Serializer/de-serializer (SERDES) included
• High speed performance
• Clock Data Recovery (CDR) built in
– fMAX = 360MHz
– tPD = 3.0ns
– tCO = 2.9ns
– tS = 2.0ns
• Built-in programmable control logic capability
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
– Encoding / decoding
– Bit alignment
• I/O intensive: 64 to 256 I/Os
– Symbol alignment
• Expanded MUX capability up to 188:1 MUX
• 8B/10B support
– Bit alignment
sysCLOCK™ PLL
– Symbol alignment
• Frequency synthesis and skew management
• Source Synchronous support
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
Flexible Programming and Testing
• Up to four PLLs
• IEEE 1532 compliant In-System Programmabil-
ity (ISP™)
sysIO™ Interfacing
• Boundary scan test through IEEE 1149.1
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
interface
standard board interfaces
• 3.3V, 2.5V or 1.8V power supplies
• SSTL 2/3 Class I and II support
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• HSTL Class I, III and IV support
interfaces
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os 64 128 256
GDX Blocks
4 8 16
tPD
tS
tCO
fMAX (Toggle)
Max Bandwidth
sysHSI Channels2
SERDES1, 2
Without SERDES3
3.0ns
2.0ns
2.9ns
360MHz
3.2Gbps
11Gbps
4
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
LVDS/Bus LVDS (Pairs)
32 64 128
PLLs
224
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13




LX128EB pdf, 반도체, 판매, 대치품
Lattice Semiconductor
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
MUX and Register Block (MRB)
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be configured as edge-triggered D-type flip-flop or as a level sensitive
latch. One register operates on the input data, the other output data and the last register synchronizes the output
enable function. The input and output data signals can bypass each of their registers. The polarity of the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock
and clock enable. The initialization signals of each register can be independently configured as Set or Reset. These
registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register
input can be set either by one of the two output enables generated locally from the Control Array or from one of the
four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has
access to Global Clock, Clock Enable, Reset and TOE nets.
4

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LX128EB 전자부품, 판매, 대치품
Lattice Semiconductor
Figure 4. ispGDX2 Family Control Array
32 Inputs from Control GRP
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
Each connection
is programmable.
MUX Select
to Nibble 0
MUX Select
to Nibble 1
MUX Select
to Nibble 2
MUX Select
to Nibble 3
To MRB Clock/
Clock Enable
On selected blocks,
this signal can reset
the M Divider of the
PLL.
To MRB
Set/Reset
To MRB
Output Enable
sysIO Banks
The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of sup-
porting different I/O standards. The number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices
respectively. Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF), allowing each
bank complete independence from the other banks. Each I/O within a bank can be individually configured to any
standard consistent with the VCCO and VREF settings. Figure 5 shows the I/O banks for the ispGDX2-256 device.
The I/O of the ispGDX2 devices contain a programmable strength and slew rate tri-state output buffer, a program-
mable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-
keeper latch. These programmable capabilities allow the support of a wide range of I/O standards.
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