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PDF SL1461SA Data sheet ( Hoja de datos )
| Número de pieza | SL1461SA | |
| Descripción | Wideband PLL FM Demodulator | |
| Fabricantes | Zarlink Semiconductor | |
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SL1461SAwww.DataSheet4U.com
Wideband PLL FM Demodulator
Advance Information
The SL1461SA is a wideband PLL FM demodulator,
intended primarily for application in satellite tuners.
The device contains all elements necessary, with the
exception of external oscillator sustaining network and loop
feedback components, to form a complete PLL system
operating at frequencies up to 800MHz.
An AFC with window adjust is provided, whose output
signal can be used to correct for any frequency drift at the head
end local oscillator.
FEATURES
I Single chip PLL system for wideband FM
demodulation
I Simple low component count application
I Allows for application of threshold extension
I Fully balanced low radiation design
I High operating input sensivity
I Improved VCO stability with variations in supply or
temperature
I AGC detect and bias adjust
I 75Ω video output drive with low distortion levels
I Dynamic self biasing analog AFC
I Full ESD Protection*
* Normal ESD handling procedures should be observed
DS4358
ISSUE 1.3
Ordering Information
SL1461SA/KG/MPAS
September 1999
AFC PUMP
AFC WINDOW ADJUST
VEE
OSCILLATOR +
OSCILLATOR –
AGC BIAS
AGC OUTPUT
RF INPUT
1 16 AFC OUTPUT
2 15 VCC
3 14 VIDEO FEEDBACK +
4 13 VIDEO –
5 12 VIDEO +
6 11 VIDEO FEEDBACK –
7 10 VIDEO OUTPUT
8 9 RF INPUT
Fig.1 Pin connections - top view
APPLICATIONS
I Satellite receiver systems
I Data communications Systems
MP16
AGC BIAS 6
8
RF INPUTS 9
AGC OUTPUT 7
4
LOCAL
OSCILLATOR
5
AFC WINDOW 2
ADJUST
Fig.2 SL1461SA block diagram
14 VIDEO
FEEDBACK +
12 VIDEO +
13 VIDEO –
11 VIDEO
FEEDBACK –
10 VIDEO
OUTPUT
1 AFC PUMP
16 AFC OUTPUT
1 page  
DESIGN OF PLL LOOP PARAMETERS
RF INPUT
GAIN = KD VOLT/RAD
R1
Advance Information SL1461SA
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R2 C1
BASEBAND OUTPUT
VCO
GAIN = K0 RAD SEC/VOLT
Fig.4
The SL1461SA is normally used as a type 1 second order
loop and can be represented by the above diagram. For such
a system the following parameters apply;
1
2
and
K0KD
12
n
2
2n
where:
K0 is the VCO gain in radian seconds per volt
KD is the phase detector gain in volts per radian
n is the natural loop bandwidth
is the loop damping factor
R1 is loop amplifier input impedance
Note: K0 is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
From these factors the loop 3dB bandwidth can be determined
from the following expression;
AFC FACILITY
The SL1461SA contains an analog frequency error
detect circuit, which generates DC voltage proportional to the
integral of frequency error. If the incident RF is high then the
AFC voltage increases, if low then the voltage decreases. The
AFC voltage can then be converted by an ADC to be read by
the micro controller for frequency fine tuning; if used in an I2C
system it is recommended the device is used with either the
SP5055 or SP5056 frequency synthesiser which contains an
internal ADC readable via the I2C bus.
The voltage corresponding to frequency alignment is
arbitrary and user defined; if used with the SP5055 it is
suggested the aligned voltage is 0.375 VCC , corresponding to
the centre code of the ADC on port 6.
The AFC detect circuit contains a deadband centre
around the aligned frequency. The deadband can be adjusted
from zero window to approximately 25MHz width assuming an
oscillator dF/dV of 15MHz/V. If the incident RF is within this
window the AFC voltage does not integrate, except by
component leakage.
With reference to Fig.5; in normal operation the
demodulated video is fed to a dual comparator where it is
compared with two reference voltages, corresponding to the
extremes of the deadband, or window. These voltages are
variable and set by the window adjust input.
The comparators produce two digital outputs
corresponding to voltages above or below the voltage
window, or frequency above or below deadband. These digital
control signals are used to control a complimentary current
source pump. The current signals are then fed to the input of
an amplifier which is arranged as an integrator, so integrating
the
pulses into a DC voltage.
If the frequency is correctly aligned both the current
source and sink are disabled, therefore the DC output voltage
remains constant. There will be a small drift due to component
leakage; the maximum drift can be calculated from;
5
5 Page 
Advance Information SL1461SA
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Fig.10 Layout of demo board with component locations
11
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| PDF Descargar | [ Datasheet SL1461SA.PDF ] | |
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