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K4S643233H-FF 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K4S643233H-FF은 전자 산업 및 응용 분야에서
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기능 Mobile-SDRAM
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K4S643233H-FF 데이터시트, 핀배열, 회로
K4S643233H - F(H)E/N/G/C/L/F
Mobwilwew-.DSaDtaSRheAet4MU.com
512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA with 0.8mm ball pitch
( -FXXX : Leaded, -HXXX : Lead Free).
GENERAL DESCRIPTION
The K4S643233H is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
K4S643233H-F(H)E/N/G/C/L/F60
166MHz(CL=3)
K4S643233H-F(H)E/N/G/C/L/F75
133MHz(CL=3)
K4S643233H-F(H)E/N/G/C/L/F1H
105MHz(CL=2)
K4S643233H-F(H)E/N/G/C/L/F1L
105MHz(CL=3)*1
- F(H)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C)
- F(H)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)
Interface
LVCMOS
Package
90 FBGA
Leaded (Lead Free)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
February 2004




K4S643233H-FF pdf, 반도체, 판매, 대치품
K4S643233H - F(H)E/N/G/C/L/F
Mobwilwew-.DSaDtaSRheAet4MU.com
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1.0
Short circuit current
IOS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
50
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Min
Typ
Max Unit
Note
Supply voltage
VDD 2.7 3.0 3.6
VDDQ
2.7
3.0
3.6
V
V
Input logic high voltage
VIH
2.2
3.0 VDDQ + 0.3
V
1
Input logic low voltage
VIL -0.3 0 0.5 V
2
Output logic high voltage
VOH
2.4
-
-
V IOH = -2mA
Output logic low voltage
VOL -
- 0.4 V IOL = 2mA
Input leakage current
ILI -10 - 10 uA
3
NOTES :
1. VIH (max) = 5.3V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Clock
CCLK
-
4.0
RAS, CAS, WE, CS, CKE
CIN - 4.0
DQM
CIN - 4.0
Address
CADD
-
4.0
DQ0 ~ DQ31
COUT
-
6.0
Unit
pF
pF
pF
pF
pF
Note
February 2004

4페이지










K4S643233H-FF 전자부품, 판매, 대치품
K4S643233H - F(H)E/N/G/C/L/F
Mobwilwew-.DSaDtaSRheAet4MU.com
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
Last data in to new col. address delay tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid output data
CAS latency=3
Number of valid output data
CAS latency=2
Number of valid output data
CAS latency=1
-60
12
18
18
42
60
-
Version
-75 -1H
15 19
19 19
19 19
45 50
100
64 69
2
tRDL + tRP
1
1
1
2
1
-
Unit Note
-1L
19 ns 1
24 ns 1
24 ns 1
60 ns 1
us
84 ns 1
CLK 2
-3
CLK 2
CLK 2
CLK 4
ea 5
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
February 2004

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