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PDF ORT42G5 Data sheet ( Hoja de datos )
| Número de pieza | ORT42G5 | |
| Descripción | 0.6 to 3.7 Gbps XAUI and FC FPSCs | |
| Fabricantes | Lattice Semiconductor | |
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ORCA® ORT42G5 and ORT82G5www.DataSheet4U.com
0.6 to 3.7 Gbps
XAUI and FC FPSCs
July 2008
Data Sheet DS1027
Introduction
Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane
data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the
ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively.
Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous inter-
face with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K
usable FPGA system gates. The CDR circuitry available from Lattice’s high-speed I/O portfolio (sysHSI™), has
already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet
(GbE, 10 GbE) applications.
Designers can also use these devices to drive high-speed data transfer across buses within any generic system.
For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a
XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be
used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and
protection links between a line card and switch fabric.
The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board
or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system perfor-
mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network
designers will benefit from the backplane transceiver as a network termination device. The device supports embed-
ded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel.
The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of
SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5,
which implements four channels of SERDES with SONET scrambling and cell processing.
Table 1. ORCA ORT42G5 and ORT82G5 Family – Available FPGA Logic
Device
PFU
FPGA Max.
PFU Rows Columns Total PFUs User I/O
LUTs
EBR EBR Bits2 FPGA System
Blocks2
(K)
Gates (K)1
ORT42G5
36
36
1296
204
10,368
12
111
333-643
ORT82G5
36
36
1296
372
10,368
12
111
333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges
are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR
usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage
and four PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1027_07.0
1 page  
Lattice Semiconductor
ORCA ORT42G5 and ORTw8w2wG.D5atDaSahteaetS4Uh.ceoemt
Programmable Features
• High-performance programmable logic:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 400K usable system gates.
– Meets multiple I/O interface standards.
– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5V and 1.8V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA
sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100
Ω) is also supported for these I/Os.
• New capability to (de)multiplex I/O signals:
– New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-block Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
dently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local
SET/RESET, and data selects.
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX,
and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PAL®-like AND-OR-Invert (AOI) in each pro-
grammable logic cell.
• New 200 MHz embedded block-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be configured as:
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5 Page 
Lattice Semiconductor
ORCA ORT42G5 and ORTw8w2wG.D5atDaSahteaetS4Uh.ceoemt
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA devices, or
visit the Lattice web site at www.latticesemi.com.
ORT42G5/ORT82G5 Overview
The ORT42G5 and ORT82G5 FPSCs provide high-speed backplane transceivers combined with FPGA logic. They
are based on the 1.5V OR4E04 ORCA FPGA and have 36 x 36 arrays of Programmable Logic Cells (PLCs). The
embedded core, which contains the backplane transceivers is attached to the right side of the device and is inte-
grated directly into the FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1.
Embedded Core Overview
The embedded core portions of the ORT42G5 and ORT82G5 contain respectively four or eight Clock and Data
Recovery (CDR) macrocells and Serialize/Deserialize (SERDES) blocks and support 8b/10b (IEEE 802.3.2002)
encoded serial links. It is intended for high-speed serial backplane data transmission. Figure 1 shows the
ORT42G5 and ORT82G5 top level block diagram and the basic data flow. Boundary scan for the
ORT42G5/ORT82G5 only includes programmable I/Os and does not include any of the embedded block I/Os.
Figure 1. ORT42G5/ORT82G5 Top Level Block Diagram
0.6 Gbps
TO
3.7 Gbps
DATA
STANDARD
FPGA I/Os
ORCA
SERIES 4
FPGA LOGIC
8b/10b
BYTE-
DECODER/ENCODER
4:1 MUX/1:4 DEMUX
WIDE
AND MULTI-CHANNEL DATA
ALIGNMENT FIFOs
SERDES w/
CLOCK/DATA
RECOVERY
4 or 8 FULL-
CML DUPLEX
I/Os SERIAL
CHANNELS
0.6 Gbps
TO
3.7 Gbps
DATA
The serial channels can each operate at up to 3.7 Gbps (2.96 Gbps data rate) with a full-duplex synchronous inter-
face with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte
alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring and
contains independent 4k x 36 RAM blocks. Overviews of the various blocks in the embedded core are presented in
the following paragraphs.
Serializer and Deserializer (SERDES)
The SERDES portion of the core contains two transceiver blocks for serial data transmission at a selectable data
rate of 0.6 to 3.7 Gbps. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core
blocks and high-speed CML interfaces to the serial links.
The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-
speed (up to 3.7 Gbps) serial data. Based on data transitions, the receiver locks an analog receive PLL for each
channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock.
The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbps serial data for off-
chip communication. The transmitter generates the necessary 3.7 GHz clocks for operation from a lower speed ref-
erence clock.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ORT42G5.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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