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PDF IDT88P8344 Data sheet ( Hoja de datos )

Número de pieza IDT88P8344
Descripción SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
Fabricantes Integrated Device Technology　
Logotipo Integrated Device Technology Logotipo



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SPI EXCHANGE 4 x SPI-3 TO SPI-4
Issue 1.0
IDT88P8344
FEATURES
• Functionality
- Low speed to high speed SPI exchange device
- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction
- Per LP configurable memory allocation
- Maskable interrupts for fatal errors
- Fragment and burst length configurable per interface: min 16 bytes,
max 256 bytes
• Standard Interfaces
- Four OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64
concurrently active LPs per interface
- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256
concurrently active LPs
- SPI-4 FIFO status channel options:
• LVDS full-rate
• LVTTL eighth-rate
- Compatible with Network Processor Streaming Interface (NPSI)
NPE-Framer mode of operation
- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the
entire frequency range
- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle
- IEEE 1149.1 JTAG
- Serial or parallel microprocessor interface for control and monitoring
• Full Suite of Performance Monitoring Counters
- Number of packets
- Number of fragments
- Number of errors
- Number of bytes
• Green parts available, see ordering information
APPLICATIONS
• Ethernet transport
• SONET / SDH packet transport line cards
• Broadband aggregation
• Multi-service switches
• IP services equipment
DESCRIPTION
The IDT88P8344 is a SPI (System Packet Interface) Exchange with four SPI-
3 interfaces and one SPI-4 interface. The data that enter on the low speed
interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for
transmission over the high speed interface (SPI-4). The data that enter on the
high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and
enqueued for transmission over a low speed interface (SPI-3). A data flow
between SPI-3 and SPI-4 interfaces is accomplished with LID maps. The logical
port addresses and number of entries in the LID maps may be dynamically
configured. Various parameters of a data flow may be configured by the user
such as buffer memory size and watermarks. In a typical application, the
IDT88P8344 enables connection of multiple SPI-3 devices to a SPI-4 network
processor. In other applications SPI-3 or SPI-4 devices may be connected to
multiple SPI-3 network processors or traffic managers.
HIGH LEVEL FUNCTIONAL BLOCK DIAGRAM
SPI-3 A
64 Logical Ports
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
SPI-3 B
64 Logical Ports
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
SPI-3 C
64 Logical Ports
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
SPI-4
256
Logical
Ports
SPI-3 D
64 Logical Ports
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
JTAG IF
Uproc IF
Clock Generator
Control Path
Data Path PFP = Packet Fragment Processor
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
6370 drw01
INDUSTRIAL TEMPERATURE RANGE
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
APRIL 2006
DSC-6370/7

1 page




IDT88P8344 pdf
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
List of Tables
www.DataSheet4U.com
Table 1 – I/O types .......................................................................................................................................................................................................... 9
Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9
Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10
Table 4 – SPI-3 status interface pin definition .................................................................................................................................................................. 10
Table 5 – SPI-4 ingress interface definition ..................................................................................................................................................................... 11
Table 6 – SPI-4 egress interface definition ...................................................................................................................................................................... 11
Table 7 – Parallel microprocessor interface .................................................................................................................................................................... 12
Table 8 – Serial microprocessor interface (serial peripheral interface mode) ................................................................................................................... 12
Table 9 – Miscellaneous ................................................................................................................................................................................................ 12
Table 10 – Both attached devices start from reset status .................................................................................................................................................. 20
Table 11 – Ingress out of synch, egress in synch ........................................................................................................................................................... 20
Table 12 – Ingress in synch, egress out of synch ........................................................................................................................................................... 20
Table 13 - DIRECTION code assignment ...................................................................................................................................................................... 26
Table 14 – CK_SEL[3:0] input pin encoding ................................................................................................................................................................... 39
Table 15 - Zero margin SPI-3 timing budget ................................................................................................................................................................... 43
Table 16 - Margin check for SPI-3 timing ........................................................................................................................................................................ 43
Table 17 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46
Table 18 - Bit order within a 32-Bit data register ............................................................................................................................................................. 46
Table 19 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46
Table 20 - Bit order within a 16-Bit address register ....................................................................................................................................................... 47
Table 21 - Bit order within an 8-Bit control register .......................................................................................................................................................... 47
Table 22 - Module base address (Module_base) ........................................................................................................................................................... 47
Table 23 - Indirect access block bases for Module A, Module B, Module C, and Module D ............................................................................................. 47
Table 24 - Indirect access block bases for common module ............................................................................................................................................ 48
Table 25 - Indirect access data registers (direct accessed space) at 0x30 to 0x33 .......................................................................................................... 48
Table 26 - Indirect access address register (direct accessed space) at 0x34 to 0x35 ...................................................................................................... 48
Table 27 - Indirect access control register (direct accessed space) at 0x3F ..................................................................................................................... 48
Table 28 - Error coding table ......................................................................................................................................................................................... 49
Table 29 - Direct mapped Module A, Module B, Module C, and Module D registers ........................................................................................................ 50
Table 30 - Direct mapped other registers ....................................................................................................................................................................... 50
Table 31 - SPI-3 data capture control register (registers 0x00, 0x08, 0x10, 0x18) ......................................................................................................... 50
Table 32 - SPI-3 data Capture register (registers 0x01, 0x09, 0x11, 0x19) .................................................................................................................... 50
Table 33 - SPI-4 data insert control register (registers 0x02, 0x0A, 0x12, 0x1A) ............................................................................................................ 51
Table 34 - SPI-4 data insert register (registers 0x03, 0x0B, 0x13, 0x1B) ....................................................................................................................... 51
Table 35 - SPI-4 data capture control register (registers 0x04, 0x0C, 0x14, 0x1C) ........................................................................................................ 51
Table 36 - SPI-3 data insert control register (registers 0x05, 0x0D, 0x15, 0x1D) ........................................................................................................... 51
Table 37 - SPI-4 data capture register (registers 0x06, 0x0E, 0x16, 0x1E) .................................................................................................................... 51
Table 38 - SPI-3 data insert register (registers 0x07, 0x0F, 0x17, 0x1F) ....................................................................................................................... 51
Table 39 - Software reset register (0x20 in the direct accessed space) ........................................................................................................................... 52
Table 40 - SPI-4 status register (0x22 in the direct accessed space) ............................................................................................................................... 52
Table 41 - SPI-4 enable register (0x23 in the direct accessed space) ............................................................................................................................. 52
Table 42 - Module status register (0x24 to 0x27 in the direct accessed space) ................................................................................................................ 53
Table 43 - Module enable register (0x28 to 0x2B in the direct accessed space) ............................................................................................................. 53
Table 44 - Primary interrupt status register (0x2C in the direct accessed space) ............................................................................................................. 54
Table 45 - Secondary interrupt status register (0x2D in the direct accessed space) ........................................................................................................ 54
Table 46 - Primary interrupt enable register (0x2E in the direct accessed space) ............................................................................................................ 55
Table 47 - Secondary interrupt enable register (0x2F in the direct accessed space) ....................................................................................................... 55
Table 48 - Module A/B/C/D indirect register .................................................................................................................................................................... 56
Table 49 - SPI-3 ingress LP to LID map ......................................................................................................................................................................... 57
Table 50 - SPI-3 general configuration register (register_offset=0x00) ............................................................................................................................ 57
Table 51 - SPI-3 ingress configuration register (register_offset=0x01) ............................................................................................................................. 58
Table 52 - SPI-3 ingress fill level register (register_offset=0x02) ..................................................................................................................................... 58
Table 53 - SPI-3 ingress max fill level register (register_offset=0x03) .............................................................................................................................. 58
Table 54 - SPI-3 egress LID to LP map ......................................................................................................................................................................... 58
Table 55 - SPI-3 egress configuration register (register_offset=0x00) ............................................................................................................................. 59
Table 56 - SPI-4 ingress to SPI-3 egress flow control register (register_offset=0x01) ...................................................................................................... 59
5 APRIL 10, 2006

5 Page





IDT88P8344 arduino
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
SPI-4 (one instantiation)
in the Name column, and mapped to the OIFwstwanwd.aDrdaptainSnhaemeet4aUc.ccoordming to
For the SPI-4 interface, each pin is used differently depending whether the the mode of operation of the interface (Link to PHY).
SPI-4 is in Link mode or in PHY mode. The pin is given a generic name, shown
TABLE 5 – SPI-4 INGRESS INTERFACE DEFINITION
Generic Name Specific Name I/O type
Description
I_DCLK (P & N) SPI4_I_DCLK_P
SPI4_I_DCLK_N
I_DAT[15:0] SPI4_I_DAT_P[15:0]
(P & N)
SPI4_I_DAT_N[15:0]
I_CRTL (P & N) SPI4_I_CTRL_P
SPI4_I_CTRL_N
I_SCLK_L
SPI4_I_SCLK_P
(P & N)
SPI4_I_SCLK_N
I_STAT_L[1:0] SPI4_I_STAT_P[1:0]
(P & N)
SPI4_I_STAT_N[1:0]
I_SCLK_T
SPI4_I_SCLK_T
I_STAT_T[1:0] SPI4_I_STAT_T[1:0]
BIAS BIAS
LVDS_STA LVDS_STA
I LVDS Ingress data clock
I LVDS Ingress data bus
I LVDS Ingress control word
O LVDS Ingressstatusclock
O LVDS Ingressstatusinfo
O LVTTL Ingressstatusclock
O LVTTL Ingressstatusinfo
Analog Use an external 3K Ohm
1% resistor to VSS
I-PU LVDS(high)/LVTTL (low) status
selection (See Note below)
NOTE:
1. A hardware reset or software reset must be performed after changing the level of this pin.
Mode
Link PHY
RDCLK TDCLK
RDAT TDAT
RCTL TCTL
RSCLK TSCLK
RSTAT TSTAT
RSCLK TSCLK
RSTAT TSTAT
---------- ----------
---------- ----------
TABLE 6 – SPI-4 EGRESS INTERFACE DEFINITION
Generic Name Specific Name I/O type
Description
E_DCLK (P & N) SPI4_E_DCLK_P
O LVDS Egress data clock
SPI4_E_DCLK_N
E_DAT[15:0] SPI4_E_DAT_P[15:0] O LVDS Egress data bus
(P & N)
SPI4_E_DAT_N[15:0]
E_CRTL (P & N) SPI4_E_CTRL_P
O LVDS Egress control word
SPI4_E_CTRL_N
E_SCLK_L
SPI4_E_SCLK_P
I LVDS Egressstatusclock
(P & N)
SPI4_E_SCLK_N
E_STAT_L[1:0] SPI4_E_STAT_P[1:0] I LVDS Egressstatusinfo
(P & N)
SPI4_E_STAT_N[1:0]
E_SCLK_T SPI4_E_SCLK_T I-ST LVTTL Egressstatusclock
E_STAT_T[1:0] SPI4_E_STAT_T[1:0] I-PU LVTTL Egressstatusinfo
Mode
Link PHY
TDCLK RDCLK
TDAT[15:0] RDAT[15:0]
TCTL
RCTL
TSCLK RSCLK
TSTAT[1:0] RSTAT[1:0]
TSCLK
TSTAT
RSCLK
RSTAT[1:0]
11 APRIL 10, 2006

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